Files
ppsspp/Core
Henrik RydgårdandClaude Opus 5.5 feb6caa3c4 Implement mfic and mtic
Both were no-ops, so mfic left its destination unchanged. They read and
write the interrupt enable flag that sceKernelCpuSuspendIntr/ResumeIntr
use. Only bit 0 counts for mtic, which also goes for
sceKernelCpuResumeIntr, since on hardware it's just mtic.

Adds the intr/mfic test, recorded on hardware.

Co-Authored-By: Claude Opus 5.5 (1M context) <[email protected]>
2026-09-25 11:08:13 -06:00
..
2026-09-10 15:25:47 -06:00
2026-09-25 11:08:13 -06:00
2026-09-25 11:08:13 -06:00
…
2026-09-22 20:19:57 +08:00
2026-09-22 20:19:57 +08:00
2026-09-11 21:24:18 -06:00
…
…
…
…
…
…