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x86 JIT: Sum vqmul's y and w in the interpreter's order

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They were added in a different order, so they rounded differently from
every other backend.

Co-Authored-By: Claude Opus 5.5 (1M context) <[email protected]>
This commit is contained in:
Henrik RydgårdandClaude Opus 5.5 committed 2026-09-24 12:24:43 -06:00
1 parent 1206528e45
commit eeb48b35c5
1 file changed
+14 -14
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Core/MIPS/x86/CompVFPU.cpp
+14 -14
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@@ -917,19 +917,19 @@ void Jit::Comp_VCrossQuat(MIPSOpcode op) {
ADDSS(XMM0, R(XMM1));
MOVSS(fpr.V(dregs[0]), XMM0);
// Compute Y
//d[1] = s[1] * t[3] + s[2] * t[0] + s[3] * t[1] - s[0] * t[2];
// Compute Y, summed in the interpreter's order
//d[1] = -s[0] * t[2] + s[1] * t[3] + s[2] * t[0] + s[3] * t[1];
MOVSS(XMM0, fpr.V(sregs[1]));
MULSS(XMM0, fpr.V(tregs[3]));
MOVSS(XMM1, fpr.V(sregs[0]));
MULSS(XMM1, fpr.V(tregs[2]));
SUBSS(XMM0, R(XMM1));
MOVSS(XMM1, fpr.V(sregs[2]));
MULSS(XMM1, fpr.V(tregs[0]));
ADDSS(XMM0, R(XMM1));
MOVSS(XMM1, fpr.V(sregs[3]));
MULSS(XMM1, fpr.V(tregs[1]));
ADDSS(XMM0, R(XMM1));
MOVSS(XMM1, fpr.V(sregs[0]));
MULSS(XMM1, fpr.V(tregs[2]));
SUBSS(XMM0, R(XMM1));
MOVSS(fpr.V(dregs[1]), XMM0);
// Compute Z
@@ -947,20 +947,20 @@ void Jit::Comp_VCrossQuat(MIPSOpcode op) {
ADDSS(XMM0, R(XMM1));
MOVSS(fpr.V(dregs[2]), XMM0);
// Compute W
// Compute W, summed in the interpreter's order: s[3] * t[3] - (s[0] * t[0] + s[1] * t[1] + s[2] * t[2])
//d[3] = -s[0] * t[0] - s[1] * t[1] - s[2] * t[2] + s[3] * t[3];
MOVSS(XMM0, fpr.V(sregs[3]));
MULSS(XMM0, fpr.V(tregs[3]));
MOVSS(XMM0, fpr.V(sregs[0]));
MULSS(XMM0, fpr.V(tregs[0]));
MOVSS(XMM1, fpr.V(sregs[1]));
MULSS(XMM1, fpr.V(tregs[1]));
SUBSS(XMM0, R(XMM1));
ADDSS(XMM0, R(XMM1));
MOVSS(XMM1, fpr.V(sregs[2]));
MULSS(XMM1, fpr.V(tregs[2]));
SUBSS(XMM0, R(XMM1));
MOVSS(XMM1, fpr.V(sregs[0]));
MULSS(XMM1, fpr.V(tregs[0]));
SUBSS(XMM0, R(XMM1));
MOVSS(fpr.V(dregs[3]), XMM0);
ADDSS(XMM0, R(XMM1));
MOVSS(XMM1, fpr.V(sregs[3]));
MULSS(XMM1, fpr.V(tregs[3]));
SUBSS(XMM1, R(XMM0));
MOVSS(fpr.V(dregs[3]), XMM1);
}
fpr.ReleaseSpillLocks();