diff --git a/Core/MIPS/x86/CompVFPU.cpp b/Core/MIPS/x86/CompVFPU.cpp
index a0e7ae443b..03c9a5f322 100644
--- a/Core/MIPS/x86/CompVFPU.cpp
+++ b/Core/MIPS/x86/CompVFPU.cpp
@@ -917,19 +917,19 @@ void Jit::Comp_VCrossQuat(MIPSOpcode op) {
 		ADDSS(XMM0, R(XMM1));
 		MOVSS(fpr.V(dregs[0]), XMM0);
 
-		// Compute Y
-		//d[1] = s[1] * t[3] + s[2] * t[0] + s[3] * t[1] - s[0] * t[2];
+		// Compute Y, summed in the interpreter's order
+		//d[1] = -s[0] * t[2] + s[1] * t[3] + s[2] * t[0] + s[3] * t[1];
 		MOVSS(XMM0, fpr.V(sregs[1]));
 		MULSS(XMM0, fpr.V(tregs[3]));
+		MOVSS(XMM1, fpr.V(sregs[0]));
+		MULSS(XMM1, fpr.V(tregs[2]));
+		SUBSS(XMM0, R(XMM1));
 		MOVSS(XMM1, fpr.V(sregs[2]));
 		MULSS(XMM1, fpr.V(tregs[0]));
 		ADDSS(XMM0, R(XMM1));
 		MOVSS(XMM1, fpr.V(sregs[3]));
 		MULSS(XMM1, fpr.V(tregs[1]));
 		ADDSS(XMM0, R(XMM1));
-		MOVSS(XMM1, fpr.V(sregs[0]));
-		MULSS(XMM1, fpr.V(tregs[2]));
-		SUBSS(XMM0, R(XMM1));
 		MOVSS(fpr.V(dregs[1]), XMM0);
 
 		// Compute Z
@@ -947,20 +947,20 @@ void Jit::Comp_VCrossQuat(MIPSOpcode op) {
 		ADDSS(XMM0, R(XMM1));
 		MOVSS(fpr.V(dregs[2]), XMM0);
 
-		// Compute W
+		// Compute W, summed in the interpreter's order: s[3] * t[3] - (s[0] * t[0] + s[1] * t[1] + s[2] * t[2])
 		//d[3] = -s[0] * t[0] - s[1] * t[1] - s[2] * t[2] + s[3] * t[3];
-		MOVSS(XMM0, fpr.V(sregs[3]));
-		MULSS(XMM0, fpr.V(tregs[3]));
+		MOVSS(XMM0, fpr.V(sregs[0]));
+		MULSS(XMM0, fpr.V(tregs[0]));
 		MOVSS(XMM1, fpr.V(sregs[1]));
 		MULSS(XMM1, fpr.V(tregs[1]));
-		SUBSS(XMM0, R(XMM1));
+		ADDSS(XMM0, R(XMM1));
 		MOVSS(XMM1, fpr.V(sregs[2]));
 		MULSS(XMM1, fpr.V(tregs[2]));
-		SUBSS(XMM0, R(XMM1));
-		MOVSS(XMM1, fpr.V(sregs[0]));
-		MULSS(XMM1, fpr.V(tregs[0]));
-		SUBSS(XMM0, R(XMM1));
-		MOVSS(fpr.V(dregs[3]), XMM0);
+		ADDSS(XMM0, R(XMM1));
+		MOVSS(XMM1, fpr.V(sregs[3]));
+		MULSS(XMM1, fpr.V(tregs[3]));
+		SUBSS(XMM1, R(XMM0));
+		MOVSS(fpr.V(dregs[3]), XMM1);
 	}
 
 	fpr.ReleaseSpillLocks();