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arm64 JIT: mtvc to the VFPU condition register keeps six bits

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The other control registers were masked already; the CC path wasn't, so
a value with bits 6 or 7 set made bvt 6 and bvt 7 branch. Hardware never
sets those (cpu/vfpu/vbranch), and the IR masks them.

Co-Authored-By: Claude Fable 5.1 <[email protected]>
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Henrik RydgårdandClaude Fable 5.1 committed 2026-09-22 14:10:22 -06:00
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commit ae81a20c74
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Core/MIPS/ARM64/Arm64CompVFPU.cpp
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@@ -1128,11 +1128,12 @@ namespace MIPSComp {
}
} else if (imm < 128 + VFPU_CTRL_MAX) { //mtvc //currentMIPS->vfpuCtrl[imm - 128] = R(rt);
if (imm - 128 == VFPU_CTRL_CC) {
// Six condition bits, the rest don't stick (cpu/vfpu/vbranch).
if (gpr.IsImm(rt)) {
gpr.SetImm(MIPS_REG_VFPUCC, gpr.GetImm(rt));
gpr.SetImm(MIPS_REG_VFPUCC, gpr.GetImm(rt) & 0x3F);
} else {
gpr.MapDirtyIn(MIPS_REG_VFPUCC, rt);
MOV(gpr.R(MIPS_REG_VFPUCC), gpr.R(rt));
ANDI2R(gpr.R(MIPS_REG_VFPUCC), gpr.R(rt), 0x3F, SCRATCH1);
}
} else {
// Only some of the bits stick (the low 20 of a prefix, say), same as the IR does it.