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riscv: Stop considering bitmanip "B".

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Apparently it's not being called B anymore and B is still reserved.
This commit is contained in:
Unknown W. Brackets committed 2023-07-23 14:41:08 -07:00
1 parent e0eace505b
commit 030a27f15d
3 files changed
+9 -12
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Common/CPUDetect.h
-1
View File
@@ -109,7 +109,6 @@ struct CPUInfo {
bool RiscV_D;
bool RiscV_C;
bool RiscV_V;
bool RiscV_B;
bool RiscV_Zicsr;
bool RiscV_Zba;
bool RiscV_Zbb;
Common/RiscVCPUDetect.cpp
+5 -7
View File
@@ -194,7 +194,7 @@ void CPUInfo::Detect()
truncate_cpy(cpu_string, parser.ISAString().c_str());
// A number of CPUs support a limited set of B. It's not all U74, so we use SOC for now...
// A number of CPUs support a limited set of bitmanip. It's not all U74, so we use SOC for now...
if (parser.FirmwareMatchesCompatible("starfive,jh7110")) {
RiscV_Zba = true;
RiscV_Zbb = true;
@@ -208,7 +208,6 @@ void CPUInfo::Detect()
RiscV_D = ExtensionSupported(hwcap, 'D');
RiscV_C = ExtensionSupported(hwcap, 'C');
RiscV_V = ExtensionSupported(hwcap, 'V');
RiscV_B = ExtensionSupported(hwcap, 'B');
// We assume as in RVA20U64 that F means Zicsr is available.
RiscV_Zicsr = RiscV_F;
@@ -242,11 +241,10 @@ std::vector<std::string> CPUInfo::Features() {
{ RiscV_D, "Double" },
{ RiscV_C, "Compressed" },
{ RiscV_V, "Vector" },
{ RiscV_B, "Bitmanip" },
{ RiscV_Zba, "Zba" },
{ RiscV_Zbb, "Zbb" },
{ RiscV_Zbc, "Zbc" },
{ RiscV_Zbs, "Zbs" },
{ RiscV_Zba, "Bitmanip Zba" },
{ RiscV_Zbb, "Bitmanip Zbb" },
{ RiscV_Zbc, "Bitmanip Zbc" },
{ RiscV_Zbs, "Bitmanip Zbs" },
{ RiscV_Zicsr, "Zicsr" },
{ CPU64bit, "64-bit" },
};
Common/RiscVEmitter.cpp
+4 -4
View File
@@ -62,10 +62,10 @@ static inline bool SupportsVector() {
static inline bool SupportsBitmanip(char zbx) {
switch (zbx) {
case 'a': return cpu_info.RiscV_B || cpu_info.RiscV_Zba;
case 'b': return cpu_info.RiscV_B || cpu_info.RiscV_Zbb;
case 'c': return cpu_info.RiscV_B || cpu_info.RiscV_Zbc;
case 's': return cpu_info.RiscV_B || cpu_info.RiscV_Zbs;
case 'a': return cpu_info.RiscV_Zba;
case 'b': return cpu_info.RiscV_Zbb;
case 'c': return cpu_info.RiscV_Zbc;
case 's': return cpu_info.RiscV_Zbs;
default: return false;
}
}