diff --git a/Common/CPUDetect.h b/Common/CPUDetect.h
index 1feb20483f..d6ae56fe2e 100644
--- a/Common/CPUDetect.h
+++ b/Common/CPUDetect.h
@@ -109,7 +109,6 @@ struct CPUInfo {
 	bool RiscV_D;
 	bool RiscV_C;
 	bool RiscV_V;
-	bool RiscV_B;
 	bool RiscV_Zicsr;
 	bool RiscV_Zba;
 	bool RiscV_Zbb;
diff --git a/Common/RiscVCPUDetect.cpp b/Common/RiscVCPUDetect.cpp
index 5292637f18..5f18db8cd9 100644
--- a/Common/RiscVCPUDetect.cpp
+++ b/Common/RiscVCPUDetect.cpp
@@ -194,7 +194,7 @@ void CPUInfo::Detect()
 
 	truncate_cpy(cpu_string, parser.ISAString().c_str());
 
-	// A number of CPUs support a limited set of B.  It's not all U74, so we use SOC for now...
+	// A number of CPUs support a limited set of bitmanip.  It's not all U74, so we use SOC for now...
 	if (parser.FirmwareMatchesCompatible("starfive,jh7110")) {
 		RiscV_Zba = true;
 		RiscV_Zbb = true;
@@ -208,7 +208,6 @@ void CPUInfo::Detect()
 	RiscV_D = ExtensionSupported(hwcap, 'D');
 	RiscV_C = ExtensionSupported(hwcap, 'C');
 	RiscV_V = ExtensionSupported(hwcap, 'V');
-	RiscV_B = ExtensionSupported(hwcap, 'B');
 	// We assume as in RVA20U64 that F means Zicsr is available.
 	RiscV_Zicsr = RiscV_F;
 
@@ -242,11 +241,10 @@ std::vector<std::string> CPUInfo::Features() {
 		{ RiscV_D, "Double" },
 		{ RiscV_C, "Compressed" },
 		{ RiscV_V, "Vector" },
-		{ RiscV_B, "Bitmanip" },
-		{ RiscV_Zba, "Zba" },
-		{ RiscV_Zbb, "Zbb" },
-		{ RiscV_Zbc, "Zbc" },
-		{ RiscV_Zbs, "Zbs" },
+		{ RiscV_Zba, "Bitmanip Zba" },
+		{ RiscV_Zbb, "Bitmanip Zbb" },
+		{ RiscV_Zbc, "Bitmanip Zbc" },
+		{ RiscV_Zbs, "Bitmanip Zbs" },
 		{ RiscV_Zicsr, "Zicsr" },
 		{ CPU64bit, "64-bit" },
 	};
diff --git a/Common/RiscVEmitter.cpp b/Common/RiscVEmitter.cpp
index 244ecf6e0c..7b201c0105 100644
--- a/Common/RiscVEmitter.cpp
+++ b/Common/RiscVEmitter.cpp
@@ -62,10 +62,10 @@ static inline bool SupportsVector() {
 
 static inline bool SupportsBitmanip(char zbx) {
 	switch (zbx) {
-	case 'a': return cpu_info.RiscV_B || cpu_info.RiscV_Zba;
-	case 'b': return cpu_info.RiscV_B || cpu_info.RiscV_Zbb;
-	case 'c': return cpu_info.RiscV_B || cpu_info.RiscV_Zbc;
-	case 's': return cpu_info.RiscV_B || cpu_info.RiscV_Zbs;
+	case 'a': return cpu_info.RiscV_Zba;
+	case 'b': return cpu_info.RiscV_Zbb;
+	case 'c': return cpu_info.RiscV_Zbc;
+	case 's': return cpu_info.RiscV_Zbs;
 	default: return false;
 	}
 }