mirror of
https://github.com/hrydgard/ppsspp.git
synced 2026-10-01 14:58:14 +00:00
Henrik RydgårdandClaude Opus 5.5
46ae865b95
The thunk saves a fixed set of registers and MXCSR on every call. The math helpers (vrcp through vrexp2, and vrot's sincos) leave MXCSR alone, so they now go through CallProtectedLeaf, which saves only the caller-saved registers the caches are using, around a direct call. vrot also no longer flushes everything first. x86-64 only; 32-bit x86 keeps the thunk. Co-Authored-By: Claude Opus 5.5 (1M context) <[email protected]>
141 lines
3.9 KiB
C++
141 lines
3.9 KiB
C++
// Copyright (c) 2012- PPSSPP Project.
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// This program is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation, version 2.0 or later versions.
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License 2.0 for more details.
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// A copy of the GPL 2.0 should have been included with the program.
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// If not, see http://www.gnu.org/licenses/
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// Official git repository and contact information can be found at
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// https://github.com/hrydgard/ppsspp and http://www.ppsspp.org/.
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#pragma once
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#include "ppsspp_config.h"
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#include "Common/x64Emitter.h"
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#include "Core/MIPS/MIPS.h"
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namespace X64JitConstants {
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#if PPSSPP_ARCH(AMD64)
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const Gen::X64Reg MEMBASEREG = Gen::RBX;
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const Gen::X64Reg CTXREG = Gen::R14;
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const Gen::X64Reg JITBASEREG = Gen::R15;
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#else
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const Gen::X64Reg CTXREG = Gen::EBP;
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#endif
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// This must be one of EAX, EBX, ECX, EDX as they have 8-bit subregisters.
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const Gen::X64Reg TEMPREG = Gen::EAX;
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const int NUM_MIPS_GPRS = 36;
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#if PPSSPP_ARCH(AMD64)
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const u32 NUM_X_REGS = 16;
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#elif PPSSPP_ARCH(X86)
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const u32 NUM_X_REGS = 8;
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#endif
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}
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struct MIPSCachedReg {
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Gen::OpArg location;
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bool away; // value not in source register
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bool locked;
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};
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struct X64CachedReg {
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MIPSGPReg mipsReg;
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bool dirty;
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bool free;
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bool allocLocked;
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};
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struct GPRRegCacheState {
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MIPSCachedReg regs[X64JitConstants::NUM_MIPS_GPRS];
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X64CachedReg xregs[X64JitConstants::NUM_X_REGS];
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};
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namespace MIPSComp {
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struct JitOptions;
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struct JitState;
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}
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class GPRRegCache
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{
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public:
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GPRRegCache();
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~GPRRegCache() {}
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void Start(MIPSState *mipsState, MIPSComp::JitState *js, MIPSComp::JitOptions *jo);
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void DiscardRegContentsIfCached(MIPSGPReg preg);
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void DiscardR(MIPSGPReg preg);
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void SetEmitter(Gen::XEmitter *emitter) {emit = emitter;}
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void FlushR(Gen::X64Reg reg);
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void FlushLockX(Gen::X64Reg reg) {
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FlushR(reg);
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LockX(reg);
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}
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void FlushLockX(Gen::X64Reg reg1, Gen::X64Reg reg2) {
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FlushR(reg1); FlushR(reg2);
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LockX(reg1); LockX(reg2);
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}
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void Flush();
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void FlushBeforeCall();
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// Flushes one register and reuses the register for another one. Dirtyness is implied.
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void FlushRemap(MIPSGPReg oldreg, MIPSGPReg newreg);
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int SanityCheck() const;
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void KillImmediate(MIPSGPReg preg, bool doLoad, bool makeDirty);
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void MapReg(MIPSGPReg preg, bool doLoad = true, bool makeDirty = true);
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void StoreFromRegister(MIPSGPReg preg);
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const Gen::OpArg &R(MIPSGPReg preg) const {return regs[preg].location;}
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Gen::X64Reg RX(MIPSGPReg preg) const
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{
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if (regs[preg].away && regs[preg].location.IsSimpleReg())
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return regs[preg].location.GetSimpleReg();
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_assert_msg_(false, "Not so simple - %d", preg);
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return (Gen::X64Reg)-1;
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}
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Gen::OpArg GetDefaultLocation(MIPSGPReg reg) const;
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// Register locking.
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void Lock(MIPSGPReg p1, MIPSGPReg p2 = MIPS_REG_INVALID, MIPSGPReg p3 = MIPS_REG_INVALID, MIPSGPReg p4 = MIPS_REG_INVALID);
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void LockX(int x1, int x2=0xff, int x3=0xff, int x4=0xff);
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void UnlockAll();
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void UnlockAllX();
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void SetImm(MIPSGPReg preg, u32 immValue);
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bool IsImm(MIPSGPReg preg) const;
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u32 GetImm(MIPSGPReg preg) const;
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void GetState(GPRRegCacheState &state) const;
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void RestoreState(const GPRRegCacheState& state);
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// Whether the register holds something the cache cares about: a MIPS register or a locked temp.
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bool IsXRegInUse(Gen::X64Reg reg) const {
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return !xregs[reg].free || xregs[reg].allocLocked;
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}
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MIPSState *mips_ = nullptr;
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private:
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Gen::X64Reg GetFreeXReg();
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Gen::X64Reg FindBestToSpill(bool unusedOnly, bool *clobbered);
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const Gen::X64Reg *GetAllocationOrder(int &count);
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MIPSCachedReg regs[X64JitConstants::NUM_MIPS_GPRS]{};
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X64CachedReg xregs[X64JitConstants::NUM_X_REGS]{};
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Gen::XEmitter *emit = nullptr;
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MIPSComp::JitState *js_;
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MIPSComp::JitOptions *jo_;
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};
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