mirror of
https://github.com/hrydgard/ppsspp.git
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Henrik RydgårdandClaude Opus 5.5
4fc858d6db
When a Load32, Store32, LoadFloat or StoreFloat is followed by the same op on the next or previous word through the same base, and the base can be mapped as a pointer, emit one LDP/STP for both. A struct-copying loop runs about 24% faster; code without such pairs is unaffected. Co-Authored-By: Claude Opus 5.5 (1M context) <[email protected]>
526 lines
16 KiB
C++
526 lines
16 KiB
C++
// Copyright (c) 2023- PPSSPP Project.
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// This program is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation, version 2.0 or later versions.
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License 2.0 for more details.
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// A copy of the GPL 2.0 should have been included with the program.
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// If not, see http://www.gnu.org/licenses/
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// Official git repository and contact information can be found at
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// https://github.com/hrydgard/ppsspp and http://www.ppsspp.org/.
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#include "ppsspp_config.h"
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// In other words, PPSSPP_ARCH(ARM64) || DISASM_ALL.
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#if PPSSPP_ARCH(ARM64) || (PPSSPP_PLATFORM(WINDOWS) && !defined(__LIBRETRO__))
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#include "Core/MemMap.h"
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#include "Core/MIPS/ARM64/Arm64IRJit.h"
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#include "Core/MIPS/ARM64/Arm64IRRegCache.h"
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// This file contains compilation for load/store instructions.
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//
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// All functions should have CONDITIONAL_DISABLE, so we can narrow things down to a file quickly.
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// Currently known non working ones should have DISABLE. No flags because that's in IR already.
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// #define CONDITIONAL_DISABLE { CompIR_Generic(inst); return; }
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#define CONDITIONAL_DISABLE {}
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#define DISABLE { CompIR_Generic(inst); return; }
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#define INVALIDOP { _assert_msg_(false, "Invalid IR inst %d", (int)inst.op); CompIR_Generic(inst); return; }
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namespace MIPSComp {
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using namespace Arm64Gen;
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using namespace Arm64IRJitConstants;
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static int IROpToByteWidth(IROp op) {
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switch (op) {
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case IROp::Load8:
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case IROp::Load8Ext:
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case IROp::Store8:
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return 1;
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case IROp::Load16:
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case IROp::Load16Ext:
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case IROp::Store16:
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return 2;
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case IROp::Load32:
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case IROp::Load32Linked:
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case IROp::Load32Left:
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case IROp::Load32Right:
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case IROp::LoadFloat:
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case IROp::Store32:
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case IROp::Store32Conditional:
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case IROp::Store32Left:
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case IROp::Store32Right:
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case IROp::StoreFloat:
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return 4;
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case IROp::LoadVec4:
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case IROp::StoreVec4:
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return 16;
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default:
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_assert_msg_(false, "Unexpected op: %s", GetIRMeta(op) ? GetIRMeta(op)->name : "?");
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return -1;
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}
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}
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Arm64JitBackend::LoadStoreArg Arm64JitBackend::PrepareSrc1Address(IRInst inst) {
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const IRMeta *m = GetIRMeta(inst.op);
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bool src1IsPointer = regs_.IsGPRMappedAsPointer(inst.src1);
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bool readsFromSrc1 = inst.src1 == inst.src3 && (m->flags & (IRFLAG_SRC3 | IRFLAG_SRC3DST)) != 0;
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// If it's about to be clobbered, don't waste time pointerifying. Use displacement.
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bool clobbersSrc1 = !readsFromSrc1 && regs_.IsGPRClobbered(inst.src1);
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int64_t imm = (int32_t)inst.constant;
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// It can't be this negative, must be a constant address with the top bit set.
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if ((imm & 0xC0000000) == 0x80000000) {
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imm = (uint64_t)(uint32_t)inst.constant;
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}
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LoadStoreArg addrArg;
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if (inst.src1 == MIPS_REG_ZERO) {
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// The constant gets applied later.
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addrArg.base = MEMBASEREG;
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#ifdef MASKED_PSP_MEMORY
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imm &= Memory::MEMVIEW32_MASK;
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#endif
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} else if (!jo.enablePointerify && readsFromSrc1) {
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#ifndef MASKED_PSP_MEMORY
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if (imm == 0) {
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addrArg.base = MEMBASEREG;
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addrArg.regOffset = regs_.MapGPR(inst.src1);
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addrArg.useRegisterOffset = true;
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addrArg.signExtendRegOffset = false;
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}
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#endif
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// Since we can't modify src1, let's just use a temp reg while copying.
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if (!addrArg.useRegisterOffset) {
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ADDI2R(SCRATCH1, regs_.MapGPR(inst.src1), imm, SCRATCH2);
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#ifdef MASKED_PSP_MEMORY
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ANDI2R(SCRATCH1, SCRATCH1, Memory::MEMVIEW32_MASK, SCRATCH2);
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#endif
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addrArg.base = MEMBASEREG;
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addrArg.regOffset = SCRATCH1;
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addrArg.useRegisterOffset = true;
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addrArg.signExtendRegOffset = false;
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}
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} else if ((jo.cachePointers && !clobbersSrc1) || src1IsPointer) {
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// The offset gets set later.
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addrArg.base = regs_.MapGPRAsPointer(inst.src1);
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} else {
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ADDI2R(SCRATCH1, regs_.MapGPR(inst.src1), imm, SCRATCH2);
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#ifdef MASKED_PSP_MEMORY
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ANDI2R(SCRATCH1, SCRATCH1, Memory::MEMVIEW32_MASK, SCRATCH2);
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#endif
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addrArg.base = MEMBASEREG;
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addrArg.regOffset = SCRATCH1;
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addrArg.useRegisterOffset = true;
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addrArg.signExtendRegOffset = false;
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}
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// That's src1 taken care of, and possibly imm.
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// If useRegisterOffset is false, imm still needs to be accounted for.
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if (!addrArg.useRegisterOffset && imm != 0) {
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#ifdef MASKED_PSP_MEMORY
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// In case we have an address + offset reg.
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if (imm > 0)
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imm &= Memory::MEMVIEW32_MASK;
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#endif
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int scale = IROpToByteWidth(inst.op);
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if (imm > 0 && (imm & (scale - 1)) == 0 && imm <= 0xFFF * scale) {
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// Okay great, use the LDR/STR form.
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addrArg.immOffset = (int)imm;
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addrArg.useUnscaled = false;
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} else if (imm >= -256 && imm < 256) {
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// An unscaled offset (LDUR/STUR) should work fine for this range.
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addrArg.immOffset = (int)imm;
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addrArg.useUnscaled = true;
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} else {
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// No luck, we'll need to load into a register.
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MOVI2R(SCRATCH1, imm);
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addrArg.regOffset = SCRATCH1;
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addrArg.useRegisterOffset = true;
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// Careful: the register offset is only the W half, extended into the 64-bit base.
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// A negative imm here is a real displacement from a pointerified register, so it
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// has to be sign extended. A positive one may be a full 32-bit address off
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// MEMBASEREG with the top bit set, which we un-sign-extended above - SXTW would
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// just make it negative again and point us ~2GB below the memory view.
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addrArg.signExtendRegOffset = imm < 0;
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}
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}
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return addrArg;
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}
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void Arm64JitBackend::CompIR_CondStore(IRInst inst) {
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CONDITIONAL_DISABLE;
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if (inst.op != IROp::Store32Conditional)
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INVALIDOP;
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regs_.SpillLockGPR(IRREG_LLBIT, inst.src3, inst.src1);
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LoadStoreArg addrArg = PrepareSrc1Address(inst);
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ARM64Reg valueReg = regs_.MapGPR(inst.src3, MIPSMap::INIT);
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regs_.MapGPR(IRREG_LLBIT, MIPSMap::INIT);
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// TODO: Safe memory? Or enough to have crash handler + validate?
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FixupBranch condFailed = CBZ(regs_.R(IRREG_LLBIT));
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if (addrArg.useRegisterOffset) {
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STR(valueReg, addrArg.base, ArithOption(addrArg.regOffset, false, addrArg.signExtendRegOffset));
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} else if (addrArg.useUnscaled) {
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STUR(valueReg, addrArg.base, addrArg.immOffset);
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} else {
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STR(INDEX_UNSIGNED, valueReg, addrArg.base, addrArg.immOffset);
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}
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if (inst.dest != MIPS_REG_ZERO) {
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MOVI2R(regs_.R(inst.dest), 1);
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FixupBranch finish = B();
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SetJumpTarget(condFailed);
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MOVI2R(regs_.R(inst.dest), 0);
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SetJumpTarget(finish);
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} else {
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SetJumpTarget(condFailed);
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}
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}
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bool Arm64JitBackend::TryCompileLoadStorePair(IRInst inst) {
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if (compilingIndex_ + 1 >= compilingCount_ || inst.src1 == MIPS_REG_ZERO)
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return false;
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const IRInst next = compilingInsts_[compilingIndex_ + 1];
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if (next.op != inst.op || next.src1 != inst.src1)
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return false;
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const int32_t offset = (int32_t)inst.constant;
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const int32_t nextOffset = (int32_t)next.constant;
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if (nextOffset != offset + 4 && nextOffset != offset - 4)
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return false;
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// The pair's scaled 7-bit signed offset.
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const int32_t low = std::min(offset, nextOffset);
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if ((low & 3) != 0 || low < -256 || low > 252)
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return false;
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// The base must be usable as a pointer.
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if (!regs_.IsGPRMappedAsPointer(inst.src1) && (!jo.cachePointers || regs_.IsGPRClobbered(inst.src1)))
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return false;
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const bool isLoad = inst.op == IROp::Load32 || inst.op == IROp::LoadFloat;
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const bool isFloat = inst.op == IROp::LoadFloat || inst.op == IROp::StoreFloat;
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// A load may not change the base, and an LDP can't write one register twice.
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if (isLoad && (next.dest == inst.dest || (!isFloat && (inst.dest == inst.src1 || next.dest == inst.src1))))
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return false;
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// Nor can a stored value be the base, which is mapped as a pointer.
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if (!isLoad && !isFloat && (inst.src3 == inst.src1 || next.src3 == inst.src1))
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return false;
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const IRReg regLow = offset < nextOffset ? inst.dest : next.dest;
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const IRReg regHigh = offset < nextOffset ? next.dest : inst.dest;
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if (isFloat) {
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regs_.SpillLockFPR(regLow, regHigh);
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regs_.SpillLockGPR(inst.src1);
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} else {
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regs_.SpillLockGPR(inst.src1, regLow, regHigh);
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}
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ARM64Reg base = regs_.MapGPRAsPointer(inst.src1);
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if (isFloat) {
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MIPSMap flags = isLoad ? MIPSMap::NOINIT : MIPSMap::INIT;
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regs_.MapFPR(regLow, flags);
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regs_.MapFPR(regHigh, flags);
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if (isLoad)
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fp_.LDP(32, INDEX_SIGNED, regs_.F(regLow), regs_.F(regHigh), base, low);
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else
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fp_.STP(32, INDEX_SIGNED, regs_.F(regLow), regs_.F(regHigh), base, low);
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} else if (isLoad) {
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regs_.MapGPR(regLow, MIPSMap::NOINIT);
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regs_.MapGPR(regHigh, MIPSMap::NOINIT);
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LDP(INDEX_SIGNED, regs_.R(regLow), regs_.R(regHigh), base, low);
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} else {
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ARM64Reg valueLow = regs_.MapGPR(regLow);
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ARM64Reg valueHigh = regs_.MapGPR(regHigh);
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STP(INDEX_SIGNED, valueLow, valueHigh, base, low);
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}
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skipNextInst_ = true;
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return true;
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}
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void Arm64JitBackend::CompIR_FLoad(IRInst inst) {
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CONDITIONAL_DISABLE;
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if (inst.op == IROp::LoadFloat && TryCompileLoadStorePair(inst))
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return;
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LoadStoreArg addrArg = PrepareSrc1Address(inst);
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switch (inst.op) {
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case IROp::LoadFloat:
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regs_.MapFPR(inst.dest, MIPSMap::NOINIT);
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if (addrArg.useRegisterOffset) {
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fp_.LDR(32, regs_.F(inst.dest), addrArg.base, ArithOption(addrArg.regOffset, false, addrArg.signExtendRegOffset));
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} else if (addrArg.useUnscaled) {
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fp_.LDUR(32, regs_.F(inst.dest), addrArg.base, addrArg.immOffset);
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} else {
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fp_.LDR(32, INDEX_UNSIGNED, regs_.F(inst.dest), addrArg.base, addrArg.immOffset);
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}
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break;
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default:
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INVALIDOP;
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break;
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}
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}
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void Arm64JitBackend::CompIR_FStore(IRInst inst) {
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CONDITIONAL_DISABLE;
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if (inst.op == IROp::StoreFloat && TryCompileLoadStorePair(inst))
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return;
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LoadStoreArg addrArg = PrepareSrc1Address(inst);
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switch (inst.op) {
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case IROp::StoreFloat:
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regs_.MapFPR(inst.src3);
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if (addrArg.useRegisterOffset) {
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fp_.STR(32, regs_.F(inst.src3), addrArg.base, ArithOption(addrArg.regOffset, false, addrArg.signExtendRegOffset));
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} else if (addrArg.useUnscaled) {
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fp_.STUR(32, regs_.F(inst.src3), addrArg.base, addrArg.immOffset);
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} else {
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fp_.STR(32, INDEX_UNSIGNED, regs_.F(inst.src3), addrArg.base, addrArg.immOffset);
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}
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break;
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default:
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INVALIDOP;
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break;
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}
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}
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void Arm64JitBackend::CompIR_Load(IRInst inst) {
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CONDITIONAL_DISABLE;
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if (inst.op == IROp::Load32 && TryCompileLoadStorePair(inst))
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return;
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regs_.SpillLockGPR(inst.dest, inst.src1);
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LoadStoreArg addrArg = PrepareSrc1Address(inst);
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// With NOINIT, MapReg won't subtract MEMBASEREG even if dest == src1.
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regs_.MapGPR(inst.dest, MIPSMap::NOINIT);
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// TODO: Safe memory? Or enough to have crash handler + validate?
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switch (inst.op) {
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case IROp::Load8:
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if (addrArg.useRegisterOffset) {
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LDRB(regs_.R(inst.dest), addrArg.base, ArithOption(addrArg.regOffset, false, addrArg.signExtendRegOffset));
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} else if (addrArg.useUnscaled) {
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LDURB(regs_.R(inst.dest), addrArg.base, addrArg.immOffset);
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} else {
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LDRB(INDEX_UNSIGNED, regs_.R(inst.dest), addrArg.base, addrArg.immOffset);
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}
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break;
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case IROp::Load8Ext:
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if (addrArg.useRegisterOffset) {
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LDRSB(regs_.R(inst.dest), addrArg.base, ArithOption(addrArg.regOffset, false, addrArg.signExtendRegOffset));
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} else if (addrArg.useUnscaled) {
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LDURSB(regs_.R(inst.dest), addrArg.base, addrArg.immOffset);
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} else {
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LDRSB(INDEX_UNSIGNED, regs_.R(inst.dest), addrArg.base, addrArg.immOffset);
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}
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break;
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case IROp::Load16:
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if (addrArg.useRegisterOffset) {
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LDRH(regs_.R(inst.dest), addrArg.base, ArithOption(addrArg.regOffset, false, addrArg.signExtendRegOffset));
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} else if (addrArg.useUnscaled) {
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LDURH(regs_.R(inst.dest), addrArg.base, addrArg.immOffset);
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} else {
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LDRH(INDEX_UNSIGNED, regs_.R(inst.dest), addrArg.base, addrArg.immOffset);
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}
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break;
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case IROp::Load16Ext:
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if (addrArg.useRegisterOffset) {
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LDRSH(regs_.R(inst.dest), addrArg.base, ArithOption(addrArg.regOffset, false, addrArg.signExtendRegOffset));
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} else if (addrArg.useUnscaled) {
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LDURSH(regs_.R(inst.dest), addrArg.base, addrArg.immOffset);
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} else {
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LDRSH(INDEX_UNSIGNED, regs_.R(inst.dest), addrArg.base, addrArg.immOffset);
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}
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break;
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case IROp::Load32:
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if (addrArg.useRegisterOffset) {
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LDR(regs_.R(inst.dest), addrArg.base, ArithOption(addrArg.regOffset, false, addrArg.signExtendRegOffset));
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} else if (addrArg.useUnscaled) {
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LDUR(regs_.R(inst.dest), addrArg.base, addrArg.immOffset);
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} else {
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LDR(INDEX_UNSIGNED, regs_.R(inst.dest), addrArg.base, addrArg.immOffset);
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}
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break;
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case IROp::Load32Linked:
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if (inst.dest != MIPS_REG_ZERO) {
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if (addrArg.useRegisterOffset) {
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LDR(regs_.R(inst.dest), addrArg.base, ArithOption(addrArg.regOffset, false, addrArg.signExtendRegOffset));
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} else if (addrArg.useUnscaled) {
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LDUR(regs_.R(inst.dest), addrArg.base, addrArg.immOffset);
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} else {
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LDR(INDEX_UNSIGNED, regs_.R(inst.dest), addrArg.base, addrArg.immOffset);
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}
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}
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regs_.SetGPRImm(IRREG_LLBIT, 1);
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break;
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default:
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INVALIDOP;
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break;
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}
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}
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void Arm64JitBackend::CompIR_LoadShift(IRInst inst) {
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CONDITIONAL_DISABLE;
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switch (inst.op) {
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case IROp::Load32Left:
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case IROp::Load32Right:
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// Should not happen if the pass to split is active.
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DISABLE;
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break;
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default:
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INVALIDOP;
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break;
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}
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}
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void Arm64JitBackend::CompIR_Store(IRInst inst) {
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CONDITIONAL_DISABLE;
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if (inst.op == IROp::Store32 && TryCompileLoadStorePair(inst))
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return;
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regs_.SpillLockGPR(inst.src3, inst.src1);
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LoadStoreArg addrArg = PrepareSrc1Address(inst);
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ARM64Reg valueReg = regs_.TryMapTempImm(inst.src3);
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if (valueReg == INVALID_REG)
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valueReg = regs_.MapGPR(inst.src3);
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// TODO: Safe memory? Or enough to have crash handler + validate?
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switch (inst.op) {
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case IROp::Store8:
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if (addrArg.useRegisterOffset) {
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STRB(valueReg, addrArg.base, ArithOption(addrArg.regOffset, false, addrArg.signExtendRegOffset));
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} else if (addrArg.useUnscaled) {
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STURB(valueReg, addrArg.base, addrArg.immOffset);
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} else {
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STRB(INDEX_UNSIGNED, valueReg, addrArg.base, addrArg.immOffset);
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}
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break;
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case IROp::Store16:
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if (addrArg.useRegisterOffset) {
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STRH(valueReg, addrArg.base, ArithOption(addrArg.regOffset, false, addrArg.signExtendRegOffset));
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} else if (addrArg.useUnscaled) {
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STURH(valueReg, addrArg.base, addrArg.immOffset);
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} else {
|
|
STRH(INDEX_UNSIGNED, valueReg, addrArg.base, addrArg.immOffset);
|
|
}
|
|
break;
|
|
|
|
case IROp::Store32:
|
|
if (addrArg.useRegisterOffset) {
|
|
STR(valueReg, addrArg.base, ArithOption(addrArg.regOffset, false, addrArg.signExtendRegOffset));
|
|
} else if (addrArg.useUnscaled) {
|
|
STUR(valueReg, addrArg.base, addrArg.immOffset);
|
|
} else {
|
|
STR(INDEX_UNSIGNED, valueReg, addrArg.base, addrArg.immOffset);
|
|
}
|
|
break;
|
|
|
|
default:
|
|
INVALIDOP;
|
|
break;
|
|
}
|
|
}
|
|
|
|
void Arm64JitBackend::CompIR_StoreShift(IRInst inst) {
|
|
CONDITIONAL_DISABLE;
|
|
|
|
switch (inst.op) {
|
|
case IROp::Store32Left:
|
|
case IROp::Store32Right:
|
|
// Should not happen if the pass to split is active.
|
|
DISABLE;
|
|
break;
|
|
|
|
default:
|
|
INVALIDOP;
|
|
break;
|
|
}
|
|
}
|
|
|
|
void Arm64JitBackend::CompIR_VecLoad(IRInst inst) {
|
|
CONDITIONAL_DISABLE;
|
|
|
|
LoadStoreArg addrArg = PrepareSrc1Address(inst);
|
|
|
|
switch (inst.op) {
|
|
case IROp::LoadVec4:
|
|
regs_.MapVec4(inst.dest, MIPSMap::NOINIT);
|
|
if (addrArg.useRegisterOffset) {
|
|
fp_.LDR(128, regs_.FQ(inst.dest), addrArg.base, ArithOption(addrArg.regOffset, false, addrArg.signExtendRegOffset));
|
|
} else if (addrArg.useUnscaled) {
|
|
fp_.LDUR(128, regs_.FQ(inst.dest), addrArg.base, addrArg.immOffset);
|
|
} else {
|
|
fp_.LDR(128, INDEX_UNSIGNED, regs_.FQ(inst.dest), addrArg.base, addrArg.immOffset);
|
|
}
|
|
break;
|
|
|
|
default:
|
|
INVALIDOP;
|
|
break;
|
|
}
|
|
}
|
|
|
|
void Arm64JitBackend::CompIR_VecStore(IRInst inst) {
|
|
CONDITIONAL_DISABLE;
|
|
|
|
LoadStoreArg addrArg = PrepareSrc1Address(inst);
|
|
|
|
switch (inst.op) {
|
|
case IROp::StoreVec4:
|
|
regs_.MapVec4(inst.src3);
|
|
if (addrArg.useRegisterOffset) {
|
|
fp_.STR(128, regs_.FQ(inst.src3), addrArg.base, ArithOption(addrArg.regOffset, false, addrArg.signExtendRegOffset));
|
|
} else if (addrArg.useUnscaled) {
|
|
fp_.STUR(128, regs_.FQ(inst.src3), addrArg.base, addrArg.immOffset);
|
|
} else {
|
|
fp_.STR(128, INDEX_UNSIGNED, regs_.FQ(inst.src3), addrArg.base, addrArg.immOffset);
|
|
}
|
|
break;
|
|
|
|
default:
|
|
INVALIDOP;
|
|
break;
|
|
}
|
|
}
|
|
|
|
} // namespace MIPSComp
|
|
|
|
#endif
|