Henrik RydgårdandClaude Opus 5.5 5865a560eb ARM JITs: Mask what ctc1 writes to fcr31 ...

Only the rounding mode, flags, enables, cause, FCC and FS bits can be
written (0x0181FFFF, pspautotests cpu/fpu/fcr), as the interpreter, IR
and x86 already have it. Both ARM JITs stored the whole value.

Co-Authored-By: Claude Opus 5.5 (1M context) <[email protected]>

2026-09-29 11:09:47 -06:00

..

ArmAsm.cpp

Add a MIPSState context pointer to the JitAt call

2026-09-21 17:34:10 -06:00

ArmCompALU.cpp

MIPS: INT_MIN / -1 leaves HI at zero, like the hardware

2026-09-22 11:02:20 -06:00

ArmCompBranch.cpp

Plumb through the PC value for syscalls, so we can get better diagnostics for unresolved ones.

2026-08-15 19:14:13 +02:00

ArmCompFPU.cpp

ARM JITs: Mask what ctc1 writes to fcr31

2026-09-29 11:09:47 -06:00

ArmCompLoadStore.cpp

Implement MMIO for the JIT (by falling back to the interpreter for load/stores from kernel addresses)

2026-08-25 00:22:40 +02:00

ArmCompReplace.cpp

…

ArmCompVFPU.cpp

Remove leftovers of 32-bit ARM Windows support

2026-09-28 13:58:29 -06:00

ArmJit.cpp

Savestate: Defer operations while the GE debugger holds a list

2026-09-28 09:34:06 -06:00

ArmJit.h

VFPU: vsqrt, vrsq, vrcp and vnrcp are exact in every backend

2026-09-24 12:24:42 -06:00

ArmRegCache.cpp

Remove more vestiges of old experiments

2026-02-12 01:23:48 +01:00

ArmRegCache.h

Remove more vestiges of old experiments

2026-02-12 01:23:48 +01:00

ArmRegCacheFPU.cpp

mips/regcache: fix before check index after access data array by index

2026-04-28 10:55:55 +02:00

ArmRegCacheFPU.h

VFPU: vsqrt, vrsq, vrcp and vnrcp are exact in every backend

2026-09-24 12:24:42 -06:00