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Author SHA1 Message Date
Pierce Andjelkovic 3ebf1e3361 Update b.sh 2025-02-16 16:36:27 +11:00
Pierce Andjelkovic 1e949c8097 Fix indentation 2021-08-07 04:08:39 +10:00
Pierce Andjelkovic 9ac4931636 Fix get CPU & CPU Brand 2021-07-31 03:03:13 +10:00
Pierce Andjelkovic bd8759853b Fix ABI 2021-07-31 01:50:48 +10:00
Pierce Andjelkovic 0d0e2c44e0 Fix copied mips bugs 2021-07-29 07:47:09 +10:00
Pierce Andjelkovic c48888c5e5 Add in bit length check 2021-07-29 07:28:29 +10:00
Pierce Andjelkovic 8cb4fb83a4 temporary riscv define fix 2021-07-29 07:19:44 +10:00
Pierce Andjelkovic d452b0c1f7 No CPU part for RISC-V 2021-07-29 03:26:18 +10:00
Pierce Andjelkovic 8541c446d6 Merge branch 'master' of github.com:archanox/ppsspp-riscv 2021-07-28 21:59:11 +10:00
Pierce Andjelkovic d9a3741fcb RISC-V CPU detect 2021-07-28 21:58:56 +10:00
Pierce Andjelkovic ef571de460 Merge branch 'hrydgard:master' into master 2021-07-28 20:42:10 +10:00
Pierce Andjelkovic 43ae3539a6 Merge branch 'hrydgard:master' into master 2021-07-23 22:12:09 +10:00
Pierce Andjelkovic 6b4da9324a Merge branch 'hrydgard:master' into master 2021-07-22 17:47:20 +10:00
Pierce Andjelkovic b03b72bf6c Merge branch 'hrydgard:master' into master 2021-07-08 15:42:33 +10:00
Pierce Andjelkovic 77e578bbb8 Re-target to merged upstream changes 2021-07-01 12:01:18 +10:00
Pierce Andjelkovic f64a6a72a5 Merge branch 'hrydgard:master' into master 2021-07-01 10:27:42 +10:00
Pierce Andjelkovic 15cdea8650 Swap submodule repo to fork 2021-06-29 22:01:30 +10:00
Pierce Andjelkovic 549ad024e4 Include FakeJit in RISC-V build 2021-06-29 21:46:17 +10:00
Pierce Andjelkovic b999b9cb99 Update CMakeLists.txt 2021-06-25 04:56:43 +10:00