Rename the ARM Jit class to ArmJit

Core/HLE/ReplaceTables.cpp

@@ -788,6 +788,16 @@ static int Hook_kankabanchoutbr_download_frame() {
 	return 0;
 }
 
+#ifdef ARM
+#define JITFUNC(f) (&MIPSComp::ArmJit::f)
+#elif defined(_M_X64) || defined(_M_IX86)
+#define JITFUNC(f) (&MIPSComp::Jit::f)
+#elif defined(MIPS)
+#define JITFUNC(f) (&MIPSComp::Jit::f)
+#elif defined(PPC)
+#define JITFUNC(f) (&MIPSComp::Jit::f)
+#endif
+
 // Can either replace with C functions or functions emitted in Asm/ArmAsm.
 static const ReplacementTableEntry entries[] = {
 	// TODO: I think some games can be helped quite a bit by implementing the
@@ -818,7 +828,7 @@ static const ReplacementTableEntry entries[] = {
 	{ "strncpy", &Replace_strncpy, 0, REPFLAG_DISABLED },
 	{ "strcmp", &Replace_strcmp, 0, REPFLAG_DISABLED },
 	{ "strncmp", &Replace_strncmp, 0, REPFLAG_DISABLED },
-	{ "fabsf", &Replace_fabsf, &MIPSComp::Jit::Replace_fabsf, REPFLAG_ALLOWINLINE | REPFLAG_DISABLED },
+	{ "fabsf", &Replace_fabsf, JITFUNC(Replace_fabsf), REPFLAG_ALLOWINLINE | REPFLAG_DISABLED },
 	{ "dl_write_matrix", &Replace_dl_write_matrix, 0, REPFLAG_DISABLED }, // &MIPSComp::Jit::Replace_dl_write_matrix, REPFLAG_DISABLED },
 	{ "dl_write_matrix_2", &Replace_dl_write_matrix, 0, REPFLAG_DISABLED },
 	{ "gta_dl_write_matrix", &Replace_gta_dl_write_matrix, 0, REPFLAG_DISABLED },

Core/MIPS/ARM/ArmAsm.cpp

@@ -75,7 +75,7 @@ void DisassembleArm(const u8 *data, int size);
 
 namespace MIPSComp {
 
-void Jit::GenerateFixedCode()
+void ArmJit::GenerateFixedCode()
 {
 	enterCode = AlignCode16();
 

Core/MIPS/ARM/ArmCompALU.cpp

@@ -50,7 +50,7 @@ namespace MIPSComp
 	static u32 EvalAdd(u32 a, u32 b) { return a + b; }
 	static u32 EvalSub(u32 a, u32 b) { return a - b; }
 
-	void Jit::CompImmLogic(MIPSGPReg rs, MIPSGPReg rt, u32 uimm, void (ARMXEmitter::*arith)(ARMReg dst, ARMReg src, Operand2 op2), bool (ARMXEmitter::*tryArithI2R)(ARMReg dst, ARMReg src, u32 val), u32 (*eval)(u32 a, u32 b))
+	void ArmJit::CompImmLogic(MIPSGPReg rs, MIPSGPReg rt, u32 uimm, void (ARMXEmitter::*arith)(ARMReg dst, ARMReg src, Operand2 op2), bool (ARMXEmitter::*tryArithI2R)(ARMReg dst, ARMReg src, u32 val), u32 (*eval)(u32 a, u32 b))
 	{
 		if (gpr.IsImm(rs)) {
 			gpr.SetImm(rt, (*eval)(gpr.GetImm(rs), uimm));
@@ -63,7 +63,7 @@ namespace MIPSComp
 		}
 	}
 
-	void Jit::Comp_IType(MIPSOpcode op)
+	void ArmJit::Comp_IType(MIPSOpcode op)
 	{
 		CONDITIONAL_DISABLE;
 		s32 simm = (s32)(s16)(op & 0xFFFF);  // sign extension
@@ -141,7 +141,7 @@ namespace MIPSComp
 		}
 	}
 
-	void Jit::Comp_RType2(MIPSOpcode op)
+	void ArmJit::Comp_RType2(MIPSOpcode op)
 	{
 		CONDITIONAL_DISABLE;
 		MIPSGPReg rs = _RS;
@@ -189,7 +189,7 @@ namespace MIPSComp
 		}
 	}
 
-	void Jit::CompType3(MIPSGPReg rd, MIPSGPReg rs, MIPSGPReg rt, void (ARMXEmitter::*arith)(ARMReg dst, ARMReg rm, Operand2 rn), bool (ARMXEmitter::*tryArithI2R)(ARMReg dst, ARMReg rm, u32 val), u32 (*eval)(u32 a, u32 b), bool symmetric)
+	void ArmJit::CompType3(MIPSGPReg rd, MIPSGPReg rs, MIPSGPReg rt, void (ARMXEmitter::*arith)(ARMReg dst, ARMReg rm, Operand2 rn), bool (ARMXEmitter::*tryArithI2R)(ARMReg dst, ARMReg rm, u32 val), u32 (*eval)(u32 a, u32 b), bool symmetric)
 	{
 		if (gpr.IsImm(rs) && gpr.IsImm(rt)) {
 			gpr.SetImm(rd, (*eval)(gpr.GetImm(rs), gpr.GetImm(rt)));
@@ -224,7 +224,7 @@ namespace MIPSComp
 		(this->*arith)(gpr.R(rd), gpr.R(rs), gpr.R(rt));
 	}
 
-	void Jit::Comp_RType3(MIPSOpcode op)
+	void ArmJit::Comp_RType3(MIPSOpcode op)
 	{
 		CONDITIONAL_DISABLE;
 		MIPSGPReg rt = _RT;
@@ -449,7 +449,7 @@ namespace MIPSComp
 		}
 	}
 
-	void Jit::CompShiftImm(MIPSOpcode op, ArmGen::ShiftType shiftType, int sa)
+	void ArmJit::CompShiftImm(MIPSOpcode op, ArmGen::ShiftType shiftType, int sa)
 	{
 		MIPSGPReg rd = _RD;
 		MIPSGPReg rt = _RT;
@@ -477,7 +477,7 @@ namespace MIPSComp
 		}
 	}
 
-	void Jit::CompShiftVar(MIPSOpcode op, ArmGen::ShiftType shiftType)
+	void ArmJit::CompShiftVar(MIPSOpcode op, ArmGen::ShiftType shiftType)
 	{
 		MIPSGPReg rd = _RD;
 		MIPSGPReg rt = _RT;
@@ -492,7 +492,7 @@ namespace MIPSComp
 		MOV(gpr.R(rd), Operand2(gpr.R(rt), shiftType, SCRATCHREG1));
 	}
 
-	void Jit::Comp_ShiftType(MIPSOpcode op)
+	void ArmJit::Comp_ShiftType(MIPSOpcode op)
 	{
 		CONDITIONAL_DISABLE;
 		MIPSGPReg rs = _RS;
@@ -519,7 +519,7 @@ namespace MIPSComp
 		}
 	}
 
-	void Jit::Comp_Special3(MIPSOpcode op)
+	void ArmJit::Comp_Special3(MIPSOpcode op)
 	{
 		CONDITIONAL_DISABLE;
 
@@ -581,7 +581,7 @@ namespace MIPSComp
 		}
 	}
 
-	void Jit::Comp_Allegrex(MIPSOpcode op)
+	void ArmJit::Comp_Allegrex(MIPSOpcode op)
 	{
 		CONDITIONAL_DISABLE;
 		MIPSGPReg rt = _RT;
@@ -635,7 +635,7 @@ namespace MIPSComp
 		}
 	}
 
-	void Jit::Comp_Allegrex2(MIPSOpcode op)
+	void ArmJit::Comp_Allegrex2(MIPSOpcode op)
 	{
 		CONDITIONAL_DISABLE;
 		MIPSGPReg rt = _RT;
@@ -667,7 +667,7 @@ namespace MIPSComp
 		}
 	}
 
-	void Jit::Comp_MulDivType(MIPSOpcode op)
+	void ArmJit::Comp_MulDivType(MIPSOpcode op)
 	{
 		CONDITIONAL_DISABLE;
 		MIPSGPReg rt = _RT;

Core/MIPS/ARM/ArmCompBranch.cpp

@@ -55,7 +55,7 @@ using namespace MIPSAnalyst;
 namespace MIPSComp
 {
 
-void Jit::BranchRSRTComp(MIPSOpcode op, ArmGen::CCFlags cc, bool likely)
+void ArmJit::BranchRSRTComp(MIPSOpcode op, ArmGen::CCFlags cc, bool likely)
 {
 	if (js.inDelaySlot) {
 		ERROR_LOG_REPORT(JIT, "Branch in RSRTComp delay slot at %08x in block starting at %08x", js.compilerPC, js.blockStart);
@@ -168,7 +168,7 @@ void Jit::BranchRSRTComp(MIPSOpcode op, ArmGen::CCFlags cc, bool likely)
 }
 
 
-void Jit::BranchRSZeroComp(MIPSOpcode op, ArmGen::CCFlags cc, bool andLink, bool likely)
+void ArmJit::BranchRSZeroComp(MIPSOpcode op, ArmGen::CCFlags cc, bool andLink, bool likely)
 {
 	if (js.inDelaySlot) {
 		ERROR_LOG_REPORT(JIT, "Branch in RSZeroComp delay slot at %08x in block starting at %08x", js.compilerPC, js.blockStart);
@@ -273,7 +273,7 @@ void Jit::BranchRSZeroComp(MIPSOpcode op, ArmGen::CCFlags cc, bool andLink, bool
 }
 
 
-void Jit::Comp_RelBranch(MIPSOpcode op)
+void ArmJit::Comp_RelBranch(MIPSOpcode op)
 {
 	// The CC flags here should be opposite of the actual branch becuase they skip the branching action.
 	switch (op >> 26)
@@ -296,7 +296,7 @@ void Jit::Comp_RelBranch(MIPSOpcode op)
 	}
 }
 
-void Jit::Comp_RelBranchRI(MIPSOpcode op)
+void ArmJit::Comp_RelBranchRI(MIPSOpcode op)
 {
 	switch ((op >> 16) & 0x1F)
 	{
@@ -315,7 +315,7 @@ void Jit::Comp_RelBranchRI(MIPSOpcode op)
 }
 
 // If likely is set, discard the branch slot if NOT taken.
-void Jit::BranchFPFlag(MIPSOpcode op, ArmGen::CCFlags cc, bool likely)
+void ArmJit::BranchFPFlag(MIPSOpcode op, ArmGen::CCFlags cc, bool likely)
 {
 	if (js.inDelaySlot) {
 		ERROR_LOG_REPORT(JIT, "Branch in FPFlag delay slot at %08x in block starting at %08x", js.compilerPC, js.blockStart);
@@ -358,7 +358,7 @@ void Jit::BranchFPFlag(MIPSOpcode op, ArmGen::CCFlags cc, bool likely)
 	js.compiling = false;
 }
 
-void Jit::Comp_FPUBranch(MIPSOpcode op)
+void ArmJit::Comp_FPUBranch(MIPSOpcode op)
 {
 	switch((op >> 16) & 0x1f)
 	{
@@ -373,7 +373,7 @@ void Jit::Comp_FPUBranch(MIPSOpcode op)
 }
 
 // If likely is set, discard the branch slot if NOT taken.
-void Jit::BranchVFPUFlag(MIPSOpcode op, ArmGen::CCFlags cc, bool likely)
+void ArmJit::BranchVFPUFlag(MIPSOpcode op, ArmGen::CCFlags cc, bool likely)
 {
 	if (js.inDelaySlot) {
 		ERROR_LOG_REPORT(JIT, "Branch in VFPU delay slot at %08x in block starting at %08x", js.compilerPC, js.blockStart);
@@ -429,7 +429,7 @@ void Jit::BranchVFPUFlag(MIPSOpcode op, ArmGen::CCFlags cc, bool likely)
 	js.compiling = false;
 }
 
-void Jit::Comp_VBranch(MIPSOpcode op)
+void ArmJit::Comp_VBranch(MIPSOpcode op)
 {
 	switch ((op >> 16) & 3)
 	{
@@ -440,7 +440,7 @@ void Jit::Comp_VBranch(MIPSOpcode op)
 	}
 }
 
-void Jit::Comp_Jump(MIPSOpcode op) {
+void ArmJit::Comp_Jump(MIPSOpcode op) {
 	if (js.inDelaySlot) {
 		ERROR_LOG_REPORT(JIT, "Branch in Jump delay slot at %08x in block starting at %08x", js.compilerPC, js.blockStart);
 		return;
@@ -499,7 +499,7 @@ void Jit::Comp_Jump(MIPSOpcode op) {
 	js.compiling = false;
 }
 
-void Jit::Comp_JumpReg(MIPSOpcode op)
+void ArmJit::Comp_JumpReg(MIPSOpcode op)
 {
 	if (js.inDelaySlot) {
 		ERROR_LOG_REPORT(JIT, "Branch in JumpReg delay slot at %08x in block starting at %08x", js.compilerPC, js.blockStart);
@@ -578,7 +578,7 @@ void Jit::Comp_JumpReg(MIPSOpcode op)
 }
 
 	
-void Jit::Comp_Syscall(MIPSOpcode op)
+void ArmJit::Comp_Syscall(MIPSOpcode op)
 {
 	// If we're in a delay slot, this is off by one.
 	const int offset = js.inDelaySlot ? -1 : 0;
@@ -610,7 +610,7 @@ void Jit::Comp_Syscall(MIPSOpcode op)
 	js.compiling = false;
 }
 
-void Jit::Comp_Break(MIPSOpcode op)
+void ArmJit::Comp_Break(MIPSOpcode op)
 {
 	Comp_Generic(op);
 	WriteSyscallExit();

Core/MIPS/ARM/ArmCompFPU.cpp

@@ -47,7 +47,7 @@
 namespace MIPSComp
 {
 
-void Jit::Comp_FPU3op(MIPSOpcode op)
+void ArmJit::Comp_FPU3op(MIPSOpcode op)
 { 
 	CONDITIONAL_DISABLE;
 
@@ -85,7 +85,7 @@ void Jit::Comp_FPU3op(MIPSOpcode op)
 
 extern int logBlocks;
 
-void Jit::Comp_FPULS(MIPSOpcode op)
+void ArmJit::Comp_FPULS(MIPSOpcode op)
 {
 	CONDITIONAL_DISABLE;
 
@@ -188,7 +188,7 @@ void Jit::Comp_FPULS(MIPSOpcode op)
 	}
 }
 
-void Jit::Comp_FPUComp(MIPSOpcode op) {
+void ArmJit::Comp_FPUComp(MIPSOpcode op) {
 	CONDITIONAL_DISABLE;
 
 	int opc = op & 0xF;
@@ -253,7 +253,7 @@ void Jit::Comp_FPUComp(MIPSOpcode op) {
 	SetCC(CC_AL);
 }
 
-void Jit::Comp_FPU2op(MIPSOpcode op) {
+void ArmJit::Comp_FPU2op(MIPSOpcode op) {
 	CONDITIONAL_DISABLE;
 
 	int fs = _FS;
@@ -347,7 +347,7 @@ void Jit::Comp_FPU2op(MIPSOpcode op) {
 	}
 }
 
-void Jit::Comp_mxc1(MIPSOpcode op)
+void ArmJit::Comp_mxc1(MIPSOpcode op)
 {
 	CONDITIONAL_DISABLE;
 

Core/MIPS/ARM/ArmCompLoadStore.cpp

@@ -66,7 +66,7 @@
 
 namespace MIPSComp
 {
-	void Jit::SetR0ToEffectiveAddress(MIPSGPReg rs, s16 offset) {
+	void ArmJit::SetR0ToEffectiveAddress(MIPSGPReg rs, s16 offset) {
 		Operand2 op2;
 		if (offset) {
 			bool negated;
@@ -91,7 +91,7 @@ namespace MIPSComp
 		}
 	}
 
-	void Jit::SetCCAndR0ForSafeAddress(MIPSGPReg rs, s16 offset, ARMReg tempReg, bool reverse) {
+	void ArmJit::SetCCAndR0ForSafeAddress(MIPSGPReg rs, s16 offset, ARMReg tempReg, bool reverse) {
 		SetR0ToEffectiveAddress(rs, offset);
 
 		// There are three valid ranges.  Each one gets a bit.
@@ -126,7 +126,7 @@ namespace MIPSComp
 		SetCC(reverse ? CC_EQ : CC_GT);
 	}
 
-	void Jit::Comp_ITypeMemLR(MIPSOpcode op, bool load) {
+	void ArmJit::Comp_ITypeMemLR(MIPSOpcode op, bool load) {
 		CONDITIONAL_DISABLE;
 		int offset = (signed short)(op & 0xFFFF);
 		MIPSGPReg rt = _RT;
@@ -272,7 +272,7 @@ namespace MIPSComp
 		}
 	}
 
-	void Jit::Comp_ITypeMem(MIPSOpcode op)
+	void ArmJit::Comp_ITypeMem(MIPSOpcode op)
 	{
 		CONDITIONAL_DISABLE;
 		int offset = (signed short)(op&0xFFFF);
@@ -389,7 +389,7 @@ namespace MIPSComp
 		}
 	}
 
-	void Jit::Comp_Cache(MIPSOpcode op) {
+	void ArmJit::Comp_Cache(MIPSOpcode op) {
 		DISABLE;
 	}
 }

Core/MIPS/ARM/ArmCompReplace.cpp

@@ -23,7 +23,7 @@
 
 namespace MIPSComp {
 
-int Jit::Replace_fabsf() {
+int ArmJit::Replace_fabsf() {
 	fpr.MapDirtyIn(0, 12);
 	VABS(fpr.R(0), fpr.R(12));
 	return 4;  // Number of instructions in the MIPS function

Core/MIPS/ARM/ArmCompVFPU.cpp

@@ -79,7 +79,7 @@ namespace MIPSComp
 		return IsOverlapSafeAllowS(dreg, di, sn, sregs, tn, tregs) && sregs[di] != dreg;
 	}
 
-	void Jit::Comp_VPFX(MIPSOpcode op)
+	void ArmJit::Comp_VPFX(MIPSOpcode op)
 	{
 		CONDITIONAL_DISABLE;
 		int data = op & 0xFFFFF;
@@ -103,7 +103,7 @@ namespace MIPSComp
 		}
 	}
 
-	void Jit::ApplyPrefixST(u8 *vregs, u32 prefix, VectorSize sz) {
+	void ArmJit::ApplyPrefixST(u8 *vregs, u32 prefix, VectorSize sz) {
 		if (prefix == 0xE4)
 			return;
 
@@ -155,7 +155,7 @@ namespace MIPSComp
 		}
 	}
 
-	void Jit::GetVectorRegsPrefixD(u8 *regs, VectorSize sz, int vectorReg) {
+	void ArmJit::GetVectorRegsPrefixD(u8 *regs, VectorSize sz, int vectorReg) {
 		_assert_(js.prefixDFlag & JitState::PREFIX_KNOWN);
 
 		GetVectorRegs(regs, sz, vectorReg);
@@ -170,7 +170,7 @@ namespace MIPSComp
 		}
 	}
 
-	void Jit::ApplyPrefixD(const u8 *vregs, VectorSize sz) {
+	void ArmJit::ApplyPrefixD(const u8 *vregs, VectorSize sz) {
 		_assert_(js.prefixDFlag & JitState::PREFIX_KNOWN);
 		if (!js.prefixD)
 			return;
@@ -217,7 +217,7 @@ namespace MIPSComp
 		}
 	}
 
-	void Jit::Comp_SV(MIPSOpcode op) {
+	void ArmJit::Comp_SV(MIPSOpcode op) {
 		NEON_IF_AVAILABLE(CompNEON_SV);
 		CONDITIONAL_DISABLE;
 
@@ -322,7 +322,7 @@ namespace MIPSComp
 		}
 	}
 
-	void Jit::Comp_SVQ(MIPSOpcode op)
+	void ArmJit::Comp_SVQ(MIPSOpcode op)
 	{
 		NEON_IF_AVAILABLE(CompNEON_SVQ);
 		CONDITIONAL_DISABLE;
@@ -467,7 +467,7 @@ namespace MIPSComp
 		fpr.ReleaseSpillLocksAndDiscardTemps();
 	}
 
-	void Jit::Comp_VVectorInit(MIPSOpcode op)
+	void ArmJit::Comp_VVectorInit(MIPSOpcode op)
 	{
 		NEON_IF_AVAILABLE(CompNEON_VVectorInit);
 		CONDITIONAL_DISABLE;
@@ -504,7 +504,7 @@ namespace MIPSComp
 		fpr.ReleaseSpillLocksAndDiscardTemps();
 	}
 
-	void Jit::Comp_VIdt(MIPSOpcode op) {
+	void ArmJit::Comp_VIdt(MIPSOpcode op) {
 		NEON_IF_AVAILABLE(CompNEON_VIdt);
 
 		CONDITIONAL_DISABLE;
@@ -542,7 +542,7 @@ namespace MIPSComp
 		fpr.ReleaseSpillLocksAndDiscardTemps();
 	}
 
-	void Jit::Comp_VMatrixInit(MIPSOpcode op)
+	void ArmJit::Comp_VMatrixInit(MIPSOpcode op)
 	{
 		NEON_IF_AVAILABLE(CompNEON_VMatrixInit);
 		CONDITIONAL_DISABLE;
@@ -591,7 +591,7 @@ namespace MIPSComp
 		fpr.ReleaseSpillLocksAndDiscardTemps();
 	}
 
-	void Jit::Comp_VHdp(MIPSOpcode op) {
+	void ArmJit::Comp_VHdp(MIPSOpcode op) {
 		NEON_IF_AVAILABLE(CompNEON_VHdp);
 		CONDITIONAL_DISABLE;
 		if (js.HasUnknownPrefix()) {
@@ -634,7 +634,7 @@ namespace MIPSComp
 
 	static const float MEMORY_ALIGNED16(vavg_table[4]) = { 1.0f, 1.0f / 2.0f, 1.0f / 3.0f, 1.0f / 4.0f };
 
-	void Jit::Comp_Vhoriz(MIPSOpcode op) {
+	void ArmJit::Comp_Vhoriz(MIPSOpcode op) {
 		NEON_IF_AVAILABLE(CompNEON_Vhoriz);
 		CONDITIONAL_DISABLE;
 		if (js.HasUnknownPrefix()) {
@@ -677,7 +677,7 @@ namespace MIPSComp
 		// NOTICE_LOG(JIT, "vfad/vags at %08x, ", js.compilerPC);
 	}
 
-	void Jit::Comp_VDot(MIPSOpcode op) {
+	void ArmJit::Comp_VDot(MIPSOpcode op) {
 		NEON_IF_AVAILABLE(CompNEON_VDot);
 		CONDITIONAL_DISABLE;
 		if (js.HasUnknownPrefix()) {
@@ -714,7 +714,7 @@ namespace MIPSComp
 		fpr.ReleaseSpillLocksAndDiscardTemps();
 	}
 
-	void Jit::Comp_VecDo3(MIPSOpcode op) {
+	void ArmJit::Comp_VecDo3(MIPSOpcode op) {
 		NEON_IF_AVAILABLE(CompNEON_VecDo3);
 		CONDITIONAL_DISABLE;
 		if (js.HasUnknownPrefix()) {
@@ -874,7 +874,7 @@ namespace MIPSComp
 		fpr.ReleaseSpillLocksAndDiscardTemps();
 	}
 
-	void Jit::Comp_VV2Op(MIPSOpcode op) {
+	void ArmJit::Comp_VV2Op(MIPSOpcode op) {
 		NEON_IF_AVAILABLE(CompNEON_VV2Op);
 		CONDITIONAL_DISABLE;
 		if (js.HasUnknownPrefix()) {
@@ -1067,7 +1067,7 @@ namespace MIPSComp
 		fpr.ReleaseSpillLocksAndDiscardTemps();
 	}
 
-	void Jit::Comp_Vi2f(MIPSOpcode op) {
+	void ArmJit::Comp_Vi2f(MIPSOpcode op) {
 		NEON_IF_AVAILABLE(CompNEON_Vi2f);
 		CONDITIONAL_DISABLE;
 		if (js.HasUnknownPrefix()) {
@@ -1114,7 +1114,7 @@ namespace MIPSComp
 		fpr.ReleaseSpillLocksAndDiscardTemps();
 	}
 
-	void Jit::Comp_Vh2f(MIPSOpcode op) {
+	void ArmJit::Comp_Vh2f(MIPSOpcode op) {
 		NEON_IF_AVAILABLE(CompNEON_Vh2f);
 		CONDITIONAL_DISABLE;
 		if (js.HasUnknownPrefix()) {
@@ -1176,7 +1176,7 @@ namespace MIPSComp
 		fpr.ReleaseSpillLocksAndDiscardTemps();
 	}
 
-	void Jit::Comp_Vf2i(MIPSOpcode op) {
+	void ArmJit::Comp_Vf2i(MIPSOpcode op) {
 		NEON_IF_AVAILABLE(CompNEON_Vf2i);
 		CONDITIONAL_DISABLE;
 
@@ -1246,7 +1246,7 @@ namespace MIPSComp
 		fpr.ReleaseSpillLocksAndDiscardTemps();
 	}
 
-	void Jit::Comp_Mftv(MIPSOpcode op) {
+	void ArmJit::Comp_Mftv(MIPSOpcode op) {
 		CONDITIONAL_DISABLE;
 		NEON_IF_AVAILABLE(CompNEON_Mftv);
 
@@ -1321,7 +1321,7 @@ namespace MIPSComp
 		fpr.ReleaseSpillLocksAndDiscardTemps();
 	}
 
-	void Jit::Comp_Vmfvc(MIPSOpcode op) {
+	void ArmJit::Comp_Vmfvc(MIPSOpcode op) {
 		NEON_IF_AVAILABLE(CompNEON_Vmtvc);
 		CONDITIONAL_DISABLE;
 
@@ -1340,7 +1340,7 @@ namespace MIPSComp
 		}
 	}
 
-	void Jit::Comp_Vmtvc(MIPSOpcode op) {
+	void ArmJit::Comp_Vmtvc(MIPSOpcode op) {
 		NEON_IF_AVAILABLE(CompNEON_Vmtvc);
 		CONDITIONAL_DISABLE;
 
@@ -1367,7 +1367,7 @@ namespace MIPSComp
 		}
 	}
 
-	void Jit::Comp_Vmmov(MIPSOpcode op) {
+	void ArmJit::Comp_Vmmov(MIPSOpcode op) {
 		NEON_IF_AVAILABLE(CompNEON_Vmmov);
 		CONDITIONAL_DISABLE;
 
@@ -1405,7 +1405,7 @@ namespace MIPSComp
 		}
 	}
 
-	void Jit::Comp_VScl(MIPSOpcode op) {
+	void ArmJit::Comp_VScl(MIPSOpcode op) {
 		NEON_IF_AVAILABLE(CompNEON_VScl);
 		CONDITIONAL_DISABLE;
 		if (js.HasUnknownPrefix()) {
@@ -1455,7 +1455,7 @@ namespace MIPSComp
 		fpr.ReleaseSpillLocksAndDiscardTemps();
 	}
 
-	void Jit::Comp_Vmmul(MIPSOpcode op) {
+	void ArmJit::Comp_Vmmul(MIPSOpcode op) {
 		CONDITIONAL_DISABLE;
 		if (js.HasUnknownPrefix()) {
 			DISABLE;
@@ -1498,12 +1498,12 @@ namespace MIPSComp
 		}
 	}
 
-	void Jit::Comp_Vmscl(MIPSOpcode op) {
+	void ArmJit::Comp_Vmscl(MIPSOpcode op) {
 		NEON_IF_AVAILABLE(CompNEON_Vmscl);
 		DISABLE;
 	}
 
-	void Jit::Comp_Vtfm(MIPSOpcode op) {
+	void ArmJit::Comp_Vtfm(MIPSOpcode op) {
 		NEON_IF_AVAILABLE(CompNEON_Vtfm);
 		CONDITIONAL_DISABLE;
 		if (js.HasUnknownPrefix()) {
@@ -1564,27 +1564,27 @@ namespace MIPSComp
 		fpr.ReleaseSpillLocksAndDiscardTemps();
 	}
 
-	void Jit::Comp_VCrs(MIPSOpcode op) {
+	void ArmJit::Comp_VCrs(MIPSOpcode op) {
 		NEON_IF_AVAILABLE(CompNEON_VCrs);
 		DISABLE;
 	}
 
-	void Jit::Comp_VDet(MIPSOpcode op) {
+	void ArmJit::Comp_VDet(MIPSOpcode op) {
 		NEON_IF_AVAILABLE(CompNEON_VDet);
 		DISABLE;
 	}
 
-	void Jit::Comp_Vi2x(MIPSOpcode op) {
+	void ArmJit::Comp_Vi2x(MIPSOpcode op) {
 		NEON_IF_AVAILABLE(CompNEON_Vi2x);
 		DISABLE;
 	}
 
-	void Jit::Comp_Vx2i(MIPSOpcode op) {
+	void ArmJit::Comp_Vx2i(MIPSOpcode op) {
 		NEON_IF_AVAILABLE(CompNEON_Vx2i);
 		DISABLE;
 	}
 
-	void Jit::Comp_VCrossQuat(MIPSOpcode op) {
+	void ArmJit::Comp_VCrossQuat(MIPSOpcode op) {
 		NEON_IF_AVAILABLE(CompNEON_VCrossQuat);
 		// This op does not support prefixes anyway.
 		CONDITIONAL_DISABLE;
@@ -1665,7 +1665,7 @@ namespace MIPSComp
 		fpr.ReleaseSpillLocksAndDiscardTemps();
 	}
 
-	void Jit::Comp_Vcmp(MIPSOpcode op) {
+	void ArmJit::Comp_Vcmp(MIPSOpcode op) {
 		NEON_IF_AVAILABLE(CompNEON_Vcmp);
 		CONDITIONAL_DISABLE;
 		if (js.HasUnknownPrefix())
@@ -1853,7 +1853,7 @@ namespace MIPSComp
 		fpr.ReleaseSpillLocksAndDiscardTemps();
 	}
 
-	void Jit::Comp_Vcmov(MIPSOpcode op) {
+	void ArmJit::Comp_Vcmov(MIPSOpcode op) {
 		NEON_IF_AVAILABLE(CompNEON_Vcmov);
 		CONDITIONAL_DISABLE;
 		if (js.HasUnknownPrefix()) {
@@ -1904,7 +1904,7 @@ namespace MIPSComp
 		fpr.ReleaseSpillLocksAndDiscardTemps();
 	}
 
-	void Jit::Comp_Viim(MIPSOpcode op) {
+	void ArmJit::Comp_Viim(MIPSOpcode op) {
 		NEON_IF_AVAILABLE(CompNEON_Viim);
 		CONDITIONAL_DISABLE;
 
@@ -1919,7 +1919,7 @@ namespace MIPSComp
 		fpr.ReleaseSpillLocksAndDiscardTemps();
 	}
 
-	void Jit::Comp_Vfim(MIPSOpcode op) {
+	void ArmJit::Comp_Vfim(MIPSOpcode op) {
 		NEON_IF_AVAILABLE(CompNEON_Vfim);
 		CONDITIONAL_DISABLE;
 		if (js.HasUnknownPrefix()) {
@@ -1939,7 +1939,7 @@ namespace MIPSComp
 		fpr.ReleaseSpillLocksAndDiscardTemps();
 	}
 
-	void Jit::Comp_Vcst(MIPSOpcode op) {
+	void ArmJit::Comp_Vcst(MIPSOpcode op) {
 		NEON_IF_AVAILABLE(CompNEON_Vcst);
 		CONDITIONAL_DISABLE;
 		if (js.HasUnknownPrefix()) {
@@ -1980,7 +1980,7 @@ namespace MIPSComp
 		return sincos.out;
 	}
 
-	void Jit::CompVrotShuffle(u8 *dregs, int imm, VectorSize sz, bool negSin) {
+	void ArmJit::CompVrotShuffle(u8 *dregs, int imm, VectorSize sz, bool negSin) {
 		int n = GetNumVectorElements(sz);
 		char what[4] = {'0', '0', '0', '0'};
 		if (((imm >> 2) & 3) == (imm & 3)) {
@@ -2010,7 +2010,7 @@ namespace MIPSComp
 	// Very heavily used by FF:CC. Should be replaced by a fast approximation instead of
 	// calling the math library.
 	// Apparently this may not work on hardfp. I don't think we have any platforms using this though.
-	void Jit::Comp_VRot(MIPSOpcode op) {
+	void ArmJit::Comp_VRot(MIPSOpcode op) {
 		NEON_IF_AVAILABLE(CompNEON_VRot);
 		// VRot probably doesn't accept prefixes anyway.
 		CONDITIONAL_DISABLE;
@@ -2073,7 +2073,7 @@ namespace MIPSComp
 		fpr.ReleaseSpillLocksAndDiscardTemps();
 	}
 
-	void Jit::Comp_Vsgn(MIPSOpcode op) {
+	void ArmJit::Comp_Vsgn(MIPSOpcode op) {
 		NEON_IF_AVAILABLE(CompNEON_Vsgn);
 		CONDITIONAL_DISABLE;
 		if (js.HasUnknownPrefix()) {
@@ -2122,7 +2122,7 @@ namespace MIPSComp
 		fpr.ReleaseSpillLocksAndDiscardTemps();
 	}
 
-	void Jit::Comp_Vocp(MIPSOpcode op) {
+	void ArmJit::Comp_Vocp(MIPSOpcode op) {
 		NEON_IF_AVAILABLE(CompNEON_Vocp);
 		CONDITIONAL_DISABLE;
 		if (js.HasUnknownPrefix()) {
@@ -2168,11 +2168,11 @@ namespace MIPSComp
 		fpr.ReleaseSpillLocksAndDiscardTemps();
 	}
 
-	void Jit::Comp_ColorConv(MIPSOpcode op) {
+	void ArmJit::Comp_ColorConv(MIPSOpcode op) {
 		DISABLE;
 	}
 
-	void Jit::Comp_Vbfy(MIPSOpcode op) {
+	void ArmJit::Comp_Vbfy(MIPSOpcode op) {
 		DISABLE;
 	}
 }

Core/MIPS/ARM/ArmCompVFPUNEON.cpp

@@ -73,7 +73,7 @@ static const float one = 1.0f;
 static const float zero = 0.0f;
 
 
-void Jit::CompNEON_VecDo3(MIPSOpcode op) {
+void ArmJit::CompNEON_VecDo3(MIPSOpcode op) {
 	CONDITIONAL_DISABLE;
 	if (js.HasUnknownPrefix()) {
 		DISABLE_UNKNOWN_PREFIX;
@@ -149,7 +149,7 @@ void Jit::CompNEON_VecDo3(MIPSOpcode op) {
 
 // #define CONDITIONAL_DISABLE { fpr.ReleaseSpillLocksAndDiscardTemps(); Comp_Generic(op); return; }
 
-void Jit::CompNEON_SV(MIPSOpcode op) {
+void ArmJit::CompNEON_SV(MIPSOpcode op) {
 	CONDITIONAL_DISABLE;
 	
 	// Remember to use single lane stores here and not VLDR/VSTR - switching usage
@@ -266,7 +266,7 @@ inline int MIPS_GET_VQVT(u32 op) {
 	return (((op >> 16) & 0x1f)) | ((op & 1) << 5);
 }
 
-void Jit::CompNEON_SVQ(MIPSOpcode op) {
+void ArmJit::CompNEON_SVQ(MIPSOpcode op) {
 	CONDITIONAL_DISABLE;
 
 	int offset = (signed short)(op & 0xFFFC);
@@ -417,7 +417,7 @@ void Jit::CompNEON_SVQ(MIPSOpcode op) {
 	fpr.ReleaseSpillLocksAndDiscardTemps();
 }
 
-void Jit::CompNEON_VVectorInit(MIPSOpcode op) {
+void ArmJit::CompNEON_VVectorInit(MIPSOpcode op) {
 	CONDITIONAL_DISABLE;
 	// WARNING: No prefix support!
 	if (js.HasUnknownPrefix()) {
@@ -442,7 +442,7 @@ void Jit::CompNEON_VVectorInit(MIPSOpcode op) {
 	fpr.ReleaseSpillLocksAndDiscardTemps();
 }
 
-void Jit::CompNEON_VDot(MIPSOpcode op) {
+void ArmJit::CompNEON_VDot(MIPSOpcode op) {
 	CONDITIONAL_DISABLE;
 	if (js.HasUnknownPrefix()) {
 		DISABLE_UNKNOWN_PREFIX;
@@ -476,7 +476,7 @@ void Jit::CompNEON_VDot(MIPSOpcode op) {
 }
 
 
-void Jit::CompNEON_VHdp(MIPSOpcode op) {
+void ArmJit::CompNEON_VHdp(MIPSOpcode op) {
 	CONDITIONAL_DISABLE;
 	if (js.HasUnknownPrefix()) {
 		DISABLE_UNKNOWN_PREFIX;
@@ -488,7 +488,7 @@ void Jit::CompNEON_VHdp(MIPSOpcode op) {
 	// A bit tricky on NEON...
 }
 
-void Jit::CompNEON_VScl(MIPSOpcode op) {
+void ArmJit::CompNEON_VScl(MIPSOpcode op) {
 	CONDITIONAL_DISABLE;
 	if (js.HasUnknownPrefix()) {
 		DISABLE_UNKNOWN_PREFIX;
@@ -507,7 +507,7 @@ void Jit::CompNEON_VScl(MIPSOpcode op) {
 	fpr.ReleaseSpillLocksAndDiscardTemps();
 }
 
-void Jit::CompNEON_VV2Op(MIPSOpcode op) {
+void ArmJit::CompNEON_VV2Op(MIPSOpcode op) {
 	CONDITIONAL_DISABLE;
 	if (js.HasUnknownPrefix()) {
 		DISABLE_UNKNOWN_PREFIX;
@@ -658,7 +658,7 @@ void Jit::CompNEON_VV2Op(MIPSOpcode op) {
 	fpr.ReleaseSpillLocksAndDiscardTemps();
 }
 
-void Jit::CompNEON_Mftv(MIPSOpcode op) {
+void ArmJit::CompNEON_Mftv(MIPSOpcode op) {
 	CONDITIONAL_DISABLE;
 	int imm = op & 0xFF;
 	MIPSGPReg rt = _RT;
@@ -736,11 +736,11 @@ void Jit::CompNEON_Mftv(MIPSOpcode op) {
 	fpr.ReleaseSpillLocksAndDiscardTemps();
 }
 
-void Jit::CompNEON_Vmfvc(MIPSOpcode op) {
+void ArmJit::CompNEON_Vmfvc(MIPSOpcode op) {
 	DISABLE;
 }
 
-void Jit::CompNEON_Vmtvc(MIPSOpcode op) {
+void ArmJit::CompNEON_Vmtvc(MIPSOpcode op) {
 	CONDITIONAL_DISABLE;
 
 	int vs = _VS;
@@ -761,7 +761,7 @@ void Jit::CompNEON_Vmtvc(MIPSOpcode op) {
 	}
 }
 
-void Jit::CompNEON_VMatrixInit(MIPSOpcode op) {
+void ArmJit::CompNEON_VMatrixInit(MIPSOpcode op) {
 	CONDITIONAL_DISABLE;
 
 	MatrixSize msz = GetMtxSize(op);
@@ -822,7 +822,7 @@ void Jit::CompNEON_VMatrixInit(MIPSOpcode op) {
 	fpr.ReleaseSpillLocksAndDiscardTemps();
 }
 
-void Jit::CompNEON_Vmmov(MIPSOpcode op) {
+void ArmJit::CompNEON_Vmmov(MIPSOpcode op) {
 	CONDITIONAL_DISABLE;
 	if (_VS == _VD) {
 		// A lot of these no-op matrix moves in Wipeout... Just drop the instruction entirely.
@@ -850,7 +850,7 @@ void Jit::CompNEON_Vmmov(MIPSOpcode op) {
 	fpr.ReleaseSpillLocksAndDiscardTemps();
 }
 
-void Jit::CompNEON_Vmmul(MIPSOpcode op) {
+void ArmJit::CompNEON_Vmmul(MIPSOpcode op) {
 	CONDITIONAL_DISABLE;
 
 	MatrixSize msz = GetMtxSize(op);
@@ -889,7 +889,7 @@ void Jit::CompNEON_Vmmul(MIPSOpcode op) {
 	fpr.ReleaseSpillLocksAndDiscardTemps();
 }
 
-void Jit::CompNEON_Vmscl(MIPSOpcode op) {
+void ArmJit::CompNEON_Vmscl(MIPSOpcode op) {
 	CONDITIONAL_DISABLE;
 
 	MatrixSize msz = GetMtxSize(op);
@@ -914,7 +914,7 @@ void Jit::CompNEON_Vmscl(MIPSOpcode op) {
 	fpr.ReleaseSpillLocksAndDiscardTemps();
 }
 
-void Jit::CompNEON_Vtfm(MIPSOpcode op) {
+void ArmJit::CompNEON_Vtfm(MIPSOpcode op) {
 	CONDITIONAL_DISABLE;
 	if (js.HasUnknownPrefix()) {
 		DISABLE;
@@ -960,27 +960,27 @@ void Jit::CompNEON_Vtfm(MIPSOpcode op) {
 	fpr.ReleaseSpillLocksAndDiscardTemps();
 }
 
-void Jit::CompNEON_VCrs(MIPSOpcode op) {
+void ArmJit::CompNEON_VCrs(MIPSOpcode op) {
 	DISABLE;
 }
 
-void Jit::CompNEON_VDet(MIPSOpcode op) {
+void ArmJit::CompNEON_VDet(MIPSOpcode op) {
 	DISABLE;
 }
 
-void Jit::CompNEON_Vi2x(MIPSOpcode op) {
+void ArmJit::CompNEON_Vi2x(MIPSOpcode op) {
 	DISABLE;
 }
 
-void Jit::CompNEON_Vx2i(MIPSOpcode op) {
+void ArmJit::CompNEON_Vx2i(MIPSOpcode op) {
 	DISABLE;
 }
 
-void Jit::CompNEON_Vf2i(MIPSOpcode op) {
+void ArmJit::CompNEON_Vf2i(MIPSOpcode op) {
 	DISABLE;
 }
 
-void Jit::CompNEON_Vi2f(MIPSOpcode op) {
+void ArmJit::CompNEON_Vi2f(MIPSOpcode op) {
 	CONDITIONAL_DISABLE;
 	if (js.HasUnknownPrefix()) {
 		DISABLE;
@@ -1006,7 +1006,7 @@ void Jit::CompNEON_Vi2f(MIPSOpcode op) {
 	fpr.ReleaseSpillLocksAndDiscardTemps();
 }
 
-void Jit::CompNEON_Vh2f(MIPSOpcode op) {
+void ArmJit::CompNEON_Vh2f(MIPSOpcode op) {
 	if (!cpu_info.bHalf) {
 		// No hardware support for half-to-float, fallback to interpreter
 		// TODO: Translate the fast SSE solution to standard integer/VFP stuff
@@ -1038,7 +1038,7 @@ void Jit::CompNEON_Vh2f(MIPSOpcode op) {
 	fpr.ReleaseSpillLocksAndDiscardTemps();
 }
 
-void Jit::CompNEON_Vcst(MIPSOpcode op) {
+void ArmJit::CompNEON_Vcst(MIPSOpcode op) {
 	CONDITIONAL_DISABLE;
 	if (js.HasUnknownPrefix()) {
 		DISABLE_UNKNOWN_PREFIX;
@@ -1056,7 +1056,7 @@ void Jit::CompNEON_Vcst(MIPSOpcode op) {
 	fpr.ReleaseSpillLocksAndDiscardTemps();
 }
 
-void Jit::CompNEON_Vhoriz(MIPSOpcode op) {
+void ArmJit::CompNEON_Vhoriz(MIPSOpcode op) {
 	CONDITIONAL_DISABLE;
 	if (js.HasUnknownPrefix()) {
 		DISABLE_UNKNOWN_PREFIX;
@@ -1092,7 +1092,7 @@ void Jit::CompNEON_Vhoriz(MIPSOpcode op) {
 	fpr.ReleaseSpillLocksAndDiscardTemps();
 }
 
-void Jit::CompNEON_VRot(MIPSOpcode op) {
+void ArmJit::CompNEON_VRot(MIPSOpcode op) {
 	CONDITIONAL_DISABLE;
 
 	if (js.HasUnknownPrefix()) {
@@ -1111,7 +1111,7 @@ void Jit::CompNEON_VRot(MIPSOpcode op) {
 	fpr.ReleaseSpillLocksAndDiscardTemps();
 }
 
-void Jit::CompNEON_VIdt(MIPSOpcode op) {
+void ArmJit::CompNEON_VIdt(MIPSOpcode op) {
 	CONDITIONAL_DISABLE;
 	if (js.HasUnknownPrefix()) {
 		DISABLE_UNKNOWN_PREFIX;
@@ -1157,7 +1157,7 @@ void Jit::CompNEON_VIdt(MIPSOpcode op) {
 	fpr.ReleaseSpillLocksAndDiscardTemps();
 }
 
-void Jit::CompNEON_Vcmp(MIPSOpcode op) {
+void ArmJit::CompNEON_Vcmp(MIPSOpcode op) {
 	CONDITIONAL_DISABLE;
 	if (js.HasUnknownPrefix())
 		DISABLE;
@@ -1288,7 +1288,7 @@ void Jit::CompNEON_Vcmp(MIPSOpcode op) {
 	ORR(gpr.R(MIPS_REG_VFPUCC), gpr.R(MIPS_REG_VFPUCC), R0);
 }
 
-void Jit::CompNEON_Vcmov(MIPSOpcode op) {
+void ArmJit::CompNEON_Vcmov(MIPSOpcode op) {
 	CONDITIONAL_DISABLE;
 	if (js.HasUnknownPrefix()) {
 		DISABLE;
@@ -1331,7 +1331,7 @@ void Jit::CompNEON_Vcmov(MIPSOpcode op) {
 	fpr.ReleaseSpillLocksAndDiscardTemps();
 }
 
-void Jit::CompNEON_Viim(MIPSOpcode op) {
+void ArmJit::CompNEON_Viim(MIPSOpcode op) {
 	CONDITIONAL_DISABLE;
 	if (js.HasUnknownPrefix()) {
 		DISABLE;
@@ -1348,7 +1348,7 @@ void Jit::CompNEON_Viim(MIPSOpcode op) {
 	fpr.ReleaseSpillLocksAndDiscardTemps();
 }
 
-void Jit::CompNEON_Vfim(MIPSOpcode op) {
+void ArmJit::CompNEON_Vfim(MIPSOpcode op) {
 	CONDITIONAL_DISABLE;
 	if (js.HasUnknownPrefix()) {
 		DISABLE;
@@ -1368,7 +1368,7 @@ void Jit::CompNEON_Vfim(MIPSOpcode op) {
 }
 
 // https://code.google.com/p/bullet/source/browse/branches/PhysicsEffects/include/vecmath/neon/vectormath_neon_assembly_implementations.S?r=2488
-void Jit::CompNEON_VCrossQuat(MIPSOpcode op) {
+void ArmJit::CompNEON_VCrossQuat(MIPSOpcode op) {
 	// This op does not support prefixes anyway.
 	CONDITIONAL_DISABLE;
 	if (js.HasUnknownPrefix()) {
@@ -1411,13 +1411,13 @@ void Jit::CompNEON_VCrossQuat(MIPSOpcode op) {
 	fpr.ReleaseSpillLocksAndDiscardTemps();
 }
 
-void Jit::CompNEON_Vsgn(MIPSOpcode op) {
+void ArmJit::CompNEON_Vsgn(MIPSOpcode op) {
 	DISABLE;
 
 	// This will be a bunch of bit magic.
 }
 
-void Jit::CompNEON_Vocp(MIPSOpcode op) {
+void ArmJit::CompNEON_Vocp(MIPSOpcode op) {
 	CONDITIONAL_DISABLE;
 	if (js.HasUnknownPrefix()) {
 		DISABLE;
@@ -1434,11 +1434,11 @@ void Jit::CompNEON_Vocp(MIPSOpcode op) {
 	fpr.ReleaseSpillLocksAndDiscardTemps();
 }
 
-void Jit::CompNEON_ColorConv(MIPSOpcode op) {
+void ArmJit::CompNEON_ColorConv(MIPSOpcode op) {
 	DISABLE;
 }
 
-void Jit::CompNEON_Vbfy(MIPSOpcode op) {
+void ArmJit::CompNEON_Vbfy(MIPSOpcode op) {
 	DISABLE;
 }
 

Core/MIPS/ARM/ArmCompVFPUNEONUtil.cpp

@@ -70,11 +70,11 @@ static const float zero = 0.0f;
 	
 // On NEON, we map triples to Q registers and singles to D registers.
 // Sometimes, as when doing dot products, it matters what's in that unused reg. This zeroes it.
-void Jit::NEONMaskToSize(ARMReg vs, VectorSize sz) {
+void ArmJit::NEONMaskToSize(ARMReg vs, VectorSize sz) {
 	// TODO
 }
 
-ARMReg Jit::NEONMapPrefixST(int mipsReg, VectorSize sz, u32 prefix, int mapFlags) {
+ARMReg ArmJit::NEONMapPrefixST(int mipsReg, VectorSize sz, u32 prefix, int mapFlags) {
 	static const float constantArray[8] = { 0.f, 1.f, 2.f, 0.5f, 3.f, 1.f / 3.f, 0.25f, 1.f / 6.f };
 	static const float constantArrayNegated[8] = { -0.f, -1.f, -2.f, -0.5f, -3.f, -1.f / 3.f, -0.25f, -1.f / 6.f };
 
@@ -255,7 +255,7 @@ ARMReg Jit::NEONMapPrefixST(int mipsReg, VectorSize sz, u32 prefix, int mapFlags
 	return ar;
 }
 
-Jit::DestARMReg Jit::NEONMapPrefixD(int vreg, VectorSize sz, int mapFlags) {
+ArmJit::DestARMReg ArmJit::NEONMapPrefixD(int vreg, VectorSize sz, int mapFlags) {
 	// Inverted from the actual bits, easier to reason about 1 == write
 	int writeMask = (~(js.prefixD >> 8)) & 0xF;
 	int n = GetNumVectorElements(sz);
@@ -277,7 +277,7 @@ Jit::DestARMReg Jit::NEONMapPrefixD(int vreg, VectorSize sz, int mapFlags) {
 	return dest;
 }
 
-void Jit::NEONApplyPrefixD(DestARMReg dest) {
+void ArmJit::NEONApplyPrefixD(DestARMReg dest) {
 	// Apply clamps to dest.rd
 	int n = GetNumVectorElements(dest.sz);
 
@@ -350,7 +350,7 @@ void Jit::NEONApplyPrefixD(DestARMReg dest) {
 	}
 }
 
-Jit::MappedRegs Jit::NEONMapDirtyInIn(MIPSOpcode op, VectorSize dsize, VectorSize ssize, VectorSize tsize, bool applyPrefixes) {
+ArmJit::MappedRegs ArmJit::NEONMapDirtyInIn(MIPSOpcode op, VectorSize dsize, VectorSize ssize, VectorSize tsize, bool applyPrefixes) {
 	MappedRegs regs;
 	if (applyPrefixes) {
 		regs.vs = NEONMapPrefixS(_VS, ssize, 0);
@@ -371,7 +371,7 @@ Jit::MappedRegs Jit::NEONMapDirtyInIn(MIPSOpcode op, VectorSize dsize, VectorSiz
 	return regs;
 }
 
-Jit::MappedRegs Jit::NEONMapInIn(MIPSOpcode op, VectorSize ssize, VectorSize tsize, bool applyPrefixes) {
+ArmJit::MappedRegs ArmJit::NEONMapInIn(MIPSOpcode op, VectorSize ssize, VectorSize tsize, bool applyPrefixes) {
 	MappedRegs regs;
 	if (applyPrefixes) {
 		regs.vs = NEONMapPrefixS(_VS, ssize, 0);
@@ -385,7 +385,7 @@ Jit::MappedRegs Jit::NEONMapInIn(MIPSOpcode op, VectorSize ssize, VectorSize tsi
 	return regs;
 }
 
-Jit::MappedRegs Jit::NEONMapDirtyIn(MIPSOpcode op, VectorSize dsize, VectorSize ssize, bool applyPrefixes) {
+ArmJit::MappedRegs ArmJit::NEONMapDirtyIn(MIPSOpcode op, VectorSize dsize, VectorSize ssize, bool applyPrefixes) {
 	MappedRegs regs;
 	regs.vs = NEONMapPrefixS(_VS, ssize, 0);
 	regs.overlap = GetVectorOverlap(_VD, dsize, _VS, ssize) > 0;
@@ -394,7 +394,7 @@ Jit::MappedRegs Jit::NEONMapDirtyIn(MIPSOpcode op, VectorSize dsize, VectorSize
 }
 
 // Requires quad registers.
-void Jit::NEONTranspose4x4(ARMReg cols[4]) {
+void ArmJit::NEONTranspose4x4(ARMReg cols[4]) {
 	// 0123   _\  0426
 	// 4567    /  1537
 	VTRN(F_32, cols[0], cols[1]);   

Core/MIPS/ARM/ArmJit.cpp

@@ -62,7 +62,7 @@ void DisassembleArm(const u8 *data, int size) {
 namespace MIPSComp
 {
 
-Jit::Jit(MIPSState *mips) : blocks(mips, this), gpr(mips, &jo), fpr(mips, &js, &jo), mips_(mips)
+ArmJit::ArmJit(MIPSState *mips) : blocks(mips, this), gpr(mips, &jo), fpr(mips, &js, &jo), mips_(mips)
 { 
 	logBlocks = 0;
 	dontLogBlocks = 0;
@@ -75,7 +75,7 @@ Jit::Jit(MIPSState *mips) : blocks(mips, this), gpr(mips, &jo), fpr(mips, &js, &
 	js.startDefaultPrefix = mips_->HasDefaultPrefix();
 }
 
-void Jit::DoState(PointerWrap &p)
+void ArmJit::DoState(PointerWrap &p)
 {
 	auto s = p.Section("Jit", 1, 2);
 	if (!s)
@@ -91,7 +91,7 @@ void Jit::DoState(PointerWrap &p)
 }
 
 // This is here so the savestate matches between jit and non-jit.
-void Jit::DoDummyState(PointerWrap &p)
+void ArmJit::DoDummyState(PointerWrap &p)
 {
 	auto s = p.Section("Jit", 1, 2);
 	if (!s)
@@ -105,14 +105,14 @@ void Jit::DoDummyState(PointerWrap &p)
 	}
 }
 
-void Jit::FlushAll()
+void ArmJit::FlushAll()
 {
 	gpr.FlushAll();
 	fpr.FlushAll();
 	FlushPrefixV();
 }
 
-void Jit::FlushPrefixV()
+void ArmJit::FlushPrefixV()
 {
 	if ((js.prefixSFlag & JitState::PREFIX_DIRTY) != 0) {
 		gpr.SetRegImm(SCRATCHREG1, js.prefixS);
@@ -133,24 +133,24 @@ void Jit::FlushPrefixV()
 	}
 }
 
-void Jit::ClearCache()
+void ArmJit::ClearCache()
 {
 	blocks.Clear();
 	ClearCodeSpace();
 	GenerateFixedCode();
 }
 
-void Jit::InvalidateCache()
+void ArmJit::InvalidateCache()
 {
 	blocks.Clear();
 }
 
-void Jit::InvalidateCacheAt(u32 em_address, int length)
+void ArmJit::InvalidateCacheAt(u32 em_address, int length)
 {
 	blocks.InvalidateICache(em_address, length);
 }
 
-void Jit::EatInstruction(MIPSOpcode op) {
+void ArmJit::EatInstruction(MIPSOpcode op) {
 	MIPSInfo info = MIPSGetInfo(op);
 	if (info & DELAYSLOT) {
 		ERROR_LOG_REPORT_ONCE(ateDelaySlot, JIT, "Ate a branch op.");
@@ -164,7 +164,7 @@ void Jit::EatInstruction(MIPSOpcode op) {
 	js.downcountAmount += MIPSGetInstructionCycleEstimate(op);
 }
 
-void Jit::CompileDelaySlot(int flags)
+void ArmJit::CompileDelaySlot(int flags)
 {
 	// preserve flag around the delay slot! Maybe this is not always necessary on ARM where 
 	// we can (mostly) control whether we set the flag or not. Of course, if someone puts an slt in to the
@@ -184,7 +184,7 @@ void Jit::CompileDelaySlot(int flags)
 }
 
 
-void Jit::Compile(u32 em_address) {
+void ArmJit::Compile(u32 em_address) {
 	if (GetSpaceLeft() < 0x10000 || blocks.IsFull()) {
 		ClearCache();
 	}
@@ -220,12 +220,12 @@ void Jit::Compile(u32 em_address) {
 	}
 }
 
-void Jit::RunLoopUntil(u64 globalticks)
+void ArmJit::RunLoopUntil(u64 globalticks)
 {
 	((void (*)())enterCode)();
 }
 
-const u8 *Jit::DoJit(u32 em_address, JitBlock *b)
+const u8 *ArmJit::DoJit(u32 em_address, JitBlock *b)
 {
 	js.cancel = false;
 	js.blockStart = js.compilerPC = mips_->pc;
@@ -350,7 +350,7 @@ const u8 *Jit::DoJit(u32 em_address, JitBlock *b)
 	return b->normalEntry;
 }
 
-void Jit::AddContinuedBlock(u32 dest)
+void ArmJit::AddContinuedBlock(u32 dest)
 {
 	// The first block is the root block.  When we continue, we create proxy blocks after that.
 	if (js.lastContinuedPC == 0)
@@ -360,19 +360,19 @@ void Jit::AddContinuedBlock(u32 dest)
 	js.lastContinuedPC = dest;
 }
 
-bool Jit::DescribeCodePtr(const u8 *ptr, std::string &name)
+bool ArmJit::DescribeCodePtr(const u8 *ptr, std::string &name)
 {
 	// TODO: Not used by anything yet.
 	return false;
 }
 
-void Jit::Comp_RunBlock(MIPSOpcode op)
+void ArmJit::Comp_RunBlock(MIPSOpcode op)
 {
 	// This shouldn't be necessary, the dispatcher should catch us before we get here.
 	ERROR_LOG(JIT, "Comp_RunBlock should never be reached!");
 }
 
-bool Jit::ReplaceJalTo(u32 dest) {
+bool ArmJit::ReplaceJalTo(u32 dest) {
 	MIPSOpcode op(Memory::Read_Opcode_JIT(dest));
 	if (!MIPS_IS_REPLACEMENT(op.encoding))
 		return false;
@@ -422,7 +422,7 @@ bool Jit::ReplaceJalTo(u32 dest) {
 	return true;
 }
 
-void Jit::Comp_ReplacementFunc(MIPSOpcode op)
+void ArmJit::Comp_ReplacementFunc(MIPSOpcode op)
 {
 	// We get here if we execute the first instruction of a replaced function. This means
 	// that we do need to return to RA.
@@ -485,7 +485,7 @@ void Jit::Comp_ReplacementFunc(MIPSOpcode op)
 	}
 }
 
-void Jit::Comp_Generic(MIPSOpcode op)
+void ArmJit::Comp_Generic(MIPSOpcode op)
 {
 	FlushAll();
 	MIPSInterpretFunc func = MIPSGetInterpretFunc(op);
@@ -511,25 +511,25 @@ void Jit::Comp_Generic(MIPSOpcode op)
 	}
 }
 
-void Jit::MovFromPC(ARMReg r) {
+void ArmJit::MovFromPC(ARMReg r) {
 	LDR(r, CTXREG, offsetof(MIPSState, pc));
 }
 
-void Jit::MovToPC(ARMReg r) {
+void ArmJit::MovToPC(ARMReg r) {
 	STR(r, CTXREG, offsetof(MIPSState, pc));
 }
 
-void Jit::SaveDowncount() {
+void ArmJit::SaveDowncount() {
 	if (jo.downcountInRegister)
 		STR(DOWNCOUNTREG, CTXREG, offsetof(MIPSState, downcount));
 }
 
-void Jit::RestoreDowncount() {
+void ArmJit::RestoreDowncount() {
 	if (jo.downcountInRegister)
 		LDR(DOWNCOUNTREG, CTXREG, offsetof(MIPSState, downcount));
 }
 
-void Jit::WriteDownCount(int offset) {
+void ArmJit::WriteDownCount(int offset) {
 	if (jo.downcountInRegister) {
 		int theDowncount = js.downcountAmount + offset;
 		Operand2 op2;
@@ -558,7 +558,7 @@ void Jit::WriteDownCount(int offset) {
 }
 
 // Abuses R2
-void Jit::WriteDownCountR(ARMReg reg) {
+void ArmJit::WriteDownCountR(ARMReg reg) {
 	if (jo.downcountInRegister) {
 		SUBS(DOWNCOUNTREG, DOWNCOUNTREG, reg);
 	} else {
@@ -568,7 +568,7 @@ void Jit::WriteDownCountR(ARMReg reg) {
 	}
 }
 
-void Jit::RestoreRoundingMode(bool force) {
+void ArmJit::RestoreRoundingMode(bool force) {
 	// If the game has never set an interesting rounding mode, we can safely skip this.
 	if (g_Config.bSetRoundingMode && (force || !g_Config.bForceFlushToZero || js.hasSetRounding)) {
 		VMRS(SCRATCHREG2);
@@ -582,7 +582,7 @@ void Jit::RestoreRoundingMode(bool force) {
 	}
 }
 
-void Jit::ApplyRoundingMode(bool force) {
+void ArmJit::ApplyRoundingMode(bool force) {
 	// NOTE: Must not destory R0.
 	// If the game has never set an interesting rounding mode, we can safely skip this.
 	if (g_Config.bSetRoundingMode && (force || !g_Config.bForceFlushToZero || js.hasSetRounding)) {
@@ -632,7 +632,7 @@ void Jit::ApplyRoundingMode(bool force) {
 	}
 }
 
-void Jit::UpdateRoundingMode() {
+void ArmJit::UpdateRoundingMode() {
 	// NOTE: Must not destory R0.
 	if (g_Config.bSetRoundingMode) {
 		LDR(SCRATCHREG2, CTXREG, offsetof(MIPSState, fcr31));
@@ -662,7 +662,7 @@ void Jit::UpdateRoundingMode() {
 // and just have conditional that set PC "twice". This only works when we fall back to dispatcher
 // though, as we need to have the SUBS flag set in the end. So with block linking in the mix,
 // I don't think this gives us that much benefit.
-void Jit::WriteExit(u32 destination, int exit_num)
+void ArmJit::WriteExit(u32 destination, int exit_num)
 {
 	WriteDownCount(); 
 	//If nobody has taken care of this yet (this can be removed when all branches are done)
@@ -682,7 +682,7 @@ void Jit::WriteExit(u32 destination, int exit_num)
 	}
 }
 
-void Jit::WriteExitDestInR(ARMReg Reg) 
+void ArmJit::WriteExitDestInR(ARMReg Reg) 
 {
 	MovToPC(Reg);
 	WriteDownCount();
@@ -690,13 +690,13 @@ void Jit::WriteExitDestInR(ARMReg Reg)
 	B((const void *)dispatcher);
 }
 
-void Jit::WriteSyscallExit()
+void ArmJit::WriteSyscallExit()
 {
 	WriteDownCount();
 	B((const void *)dispatcherCheckCoreState);
 }
 
-void Jit::Comp_DoNothing(MIPSOpcode op) { }
+void ArmJit::Comp_DoNothing(MIPSOpcode op) { }
 
 #define _RS ((op>>21) & 0x1F)
 #define _RT ((op>>16) & 0x1F)

Core/MIPS/ARM/ArmJit.h

@@ -61,10 +61,10 @@ struct ArmJitOptions
 	int continueMaxInstructions;
 };
 
-class Jit : public ArmGen::ARMXCodeBlock
+class ArmJit : public ArmGen::ARMXCodeBlock
 {
 public:
-	Jit(MIPSState *mips);
+	ArmJit(MIPSState *mips);
 
 	void DoState(PointerWrap &p);
 	static void DoDummyState(PointerWrap &p);
@@ -324,8 +324,8 @@ public:
 	const u8 *breakpointBailout;
 };
 
-typedef void (Jit::*MIPSCompileFunc)(MIPSOpcode opcode);
-typedef int (Jit::*MIPSReplaceFunc)();
+typedef void (ArmJit::*MIPSCompileFunc)(MIPSOpcode opcode);
+typedef int (ArmJit::*MIPSReplaceFunc)();
 
 }	// namespace MIPSComp
 

Core/MIPS/JitCommon/JitCommon.cpp

@@ -24,7 +24,11 @@
 #include "ext/udis86/udis86.h"
 
 namespace MIPSComp {
+#if defined(ARM)
+	ArmJit *jit;
+#else
 	Jit *jit;
+#endif
 }
 
 // We compile this for x86 as well because it may be useful when developing the ARM JIT on a PC.

Core/MIPS/JitCommon/JitCommon.h

@@ -61,7 +61,11 @@ struct JitBlock;
 #define MIPS_EMUHACK_CALL_REPLACEMENT (MIPS_EMUHACK_OPCODE | (EMUOP_CALL_REPLACEMENT << 24))
 
 namespace MIPSComp {
+#if defined(ARM)
+	extern ArmJit *jit;
+#else
 	extern Jit *jit;
+#endif
 }
 
 std::vector<std::string> DisassembleArm2(const u8 *data, int size);

Core/MIPS/MIPS.cpp

@@ -219,8 +219,13 @@ void MIPSState::Init() {
 	// Initialize the VFPU random number generator with .. something?
 	rng.Init(0x1337);
 
-	if (PSP_CoreParameter().cpuCore == CPU_JIT)
+	if (PSP_CoreParameter().cpuCore == CPU_JIT) {
+#ifdef ARM
+		MIPSComp::jit = new MIPSComp::ArmJit(this);
+#else
 		MIPSComp::jit = new MIPSComp::Jit(this);
+#endif
+	}
 }
 
 bool MIPSState::HasDefaultPrefix() const {
@@ -236,7 +241,11 @@ void MIPSState::UpdateCore(CPUCore desired) {
 	switch (PSP_CoreParameter().cpuCore) {
 	case CPU_JIT:
 		if (!MIPSComp::jit) {
+#ifdef ARM
+			MIPSComp::jit = new MIPSComp::ArmJit(this);
+#else
 			MIPSComp::jit = new MIPSComp::Jit(this);
+#endif
 		}
 		break;
 
@@ -258,7 +267,7 @@ void MIPSState::DoState(PointerWrap &p) {
 	if (MIPSComp::jit)
 		MIPSComp::jit->DoState(p);
 	else
-		MIPSComp::Jit::DoDummyState(p);
+		MIPSComp::jit->DoDummyState(p);
 
 	p.DoArray(r, sizeof(r) / sizeof(r[0]));
 	p.DoArray(f, sizeof(f) / sizeof(f[0]));

Core/MIPS/MIPSTables.cpp

@@ -89,7 +89,7 @@ struct MIPSInstruction {
 #endif
 
 #ifdef ARM
-#define JITFUNC(f) (&Jit::f)
+#define JITFUNC(f) (&ArmJit::f)
 #elif defined(_M_X64) || defined(_M_IX86)
 #define JITFUNC(f) (&Jit::f)
 #elif defined(MIPS)