Vulkan layout and barrier edits made the GPU use a different shader path that compiled a TLDS instruction with an unaligned register (R157).
The old path never generated that case, so the translator’s missing unaligned-register handling only surfaced after this change.
Co-authored-by: Ribbit <[email protected]>
Reviewed-on: https://git.eden-emu.dev/eden-emu/eden/pulls/2748
Reviewed-by: MaranBr <[email protected]>
Co-authored-by: Ribbit <[email protected]>
Co-committed-by: Ribbit <[email protected]>
Wait only at the transfer and color stages instead of every stage. That keeps things in sync without stalling the whole GPU.
This should work according to spec, just need to test and verify no regressions across all platforms (Windows, Linux, Android, Mac OS)
Can be 0.0.4 or 0.0.5 up to the team.
Co-authored-by: Ribbit <[email protected]>
Reviewed-on: https://git.eden-emu.dev/eden-emu/eden/pulls/2734
Reviewed-by: MaranBr <[email protected]>
Reviewed-by: Shinmegumi <[email protected]>
Co-authored-by: Ribbit <[email protected]>
Co-committed-by: Ribbit <[email protected]>
The barrier before the CPU-upload copy was using VK_PIPELINE_STAGE_HOST_BIT. Validation rules only allow HOST as the source stage if you’re also specifying host-side access flags; inside a command buffer the GPU isn’t executing “host work,” so pairing that stage with the usual image layout transition is technically invalid.
Switching the source stage to VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT keeps the ordering guarantee we need and satisfies the spec, while the actual host visibility is still handled correctly by the preceding vmaFlushAllocation.
Co-authored-by: Ribbit <[email protected]>
Reviewed-on: https://git.eden-emu.dev/eden-emu/eden/pulls/2681
Reviewed-by: MaranBr <[email protected]>
Reviewed-by: Shinmegumi <[email protected]>
Co-authored-by: Ribbit <[email protected]>
Co-committed-by: Ribbit <[email protected]>
Adding the shader read barrier keeps every render/compute/transfer write visible before the image is sampled, so it prevents the “read-before-writes-finish” hazards. Without it you can get random stale frames, flickering post process passes, partially updated HUD textures, and corrupted depth-to-color conversions especially in scenes that render into an offscreen image and immediately feed that image to a shader (reflections, bloom, dynamic resolution, depth visualizers, etc.). This fix makes those R2T chains deterministic again across all Vulkan drivers.
Co-authored-by: Ribbit <[email protected]>
Reviewed-on: https://git.eden-emu.dev/eden-emu/eden/pulls/2671
Reviewed-by: MaranBr <[email protected]>
Reviewed-by: crueter <[email protected]>
Co-authored-by: Ribbit <[email protected]>
Co-committed-by: Ribbit <[email protected]>
We copy pixels into a CPU-side staging buffer and then ask the GPU to read from it. On some systems those CPU writes aren’t automatically visible to the GPU unless explicitly flushed, so the GPU can sometimes read stale data. By calling buffer.Flush() immediately after writing, we force those CPU changes to become visible to the device, ensuring the GPU sees the latest frame. However, this is an emulator, so sometimes what spec says may not work cause reasons.
Co-authored-by: Ribbit <[email protected]>
Reviewed-on: https://git.eden-emu.dev/eden-emu/eden/pulls/2624
Reviewed-by: Shinmegumi <[email protected]>
Reviewed-by: MaranBr <[email protected]>
Co-authored-by: Ribbit <[email protected]>
Co-committed-by: Ribbit <[email protected]>
