[dynarmic] Fix ISB with new JIT schema (#3576)

If an ISB is issued, the changes on the memory wouldn't be reflected
Now we emulate "instruction cache" properly by just telling the mechanism to re-fetch the entire page again (to make ANY changes visible immediately)

This mainly fixes a potential issue where an ISB is emitted before a branch on the same codepage.

Signed-off-by: lizzie <[email protected]>
Reviewed-on: https://git.eden-emu.dev/eden-emu/eden/pulls/3576
Reviewed-by: CamilleLaVey <[email protected]>
Reviewed-by: crueter <[email protected]>
Reviewed-by: DraVee <[email protected]>
Co-authored-by: lizzie <[email protected]>
Co-committed-by: lizzie <[email protected]>
This commit is contained in:
lizzie authored and crueter committed 2026-02-21 01:53:48 +01:00
1 parent f76dc401c3
commit 4f29128e50
3 files changed
+9

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+3
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@@ -35,6 +35,9 @@ public:
u32 MemoryRead32(u32 vaddr) override;
u64 MemoryRead64(u32 vaddr) override;
std::optional<u32> MemoryReadCode(u32 vaddr) override;
void InstructionSynchronizationBarrierRaised() override {
last_code_addr = 0; //reset back, force refetch
}
void MemoryWrite8(u32 vaddr, u8 value) override;
void MemoryWrite16(u32 vaddr, u16 value) override;
void MemoryWrite32(u32 vaddr, u32 value) override;
+3
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@@ -42,6 +42,9 @@ public:
u64 MemoryRead64(u64 vaddr) override;
Dynarmic::A64::Vector MemoryRead128(u64 vaddr) override;
std::optional<u32> MemoryReadCode(u64 vaddr) override;
void InstructionSynchronizationBarrierRaised() override {
last_code_addr = 0; //reset back, force refetch
}
void MemoryWrite8(u64 vaddr, u8 value) override;
void MemoryWrite16(u64 vaddr, u16 value) override;
void MemoryWrite32(u64 vaddr, u32 value) override;
+3
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@@ -56,6 +56,9 @@ public:
}
return cached_code_page.inst[(vaddr & Core::Memory::YUZU_PAGEMASK) / sizeof(u32)];
}
void InstructionSynchronizationBarrierRaised() override {
last_code_addr = 0; //reset back, force refetch
}
u8 MemoryRead8(u64 vaddr) override {
return ReadMemory<u8>(vaddr);
}