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Henrik RydgårdandClaude Opus 5
bd505b7f1c
div.s now maintains fcr31's Cause.Z and (when the trap is masked) sticky Flag.Z bits, in the standard MIPS bit positions. Only a finite non-zero dividend counts, so 0/0, inf/0 and NaN operands are excluded per IEEE 754. When the guest has the trap unmasked, the new Core_FPUException() reports it with the usual module suffix and MIPS call stack, and fd is left unwritten as hardware would. That's gated behind a new developer setting, off by default: PSP threads start with fcr31 = 0x00000e00, i.e. three of the traps already enabled, and games divide by zero without meaning anything by it. The fcr31 bits are updated either way, so what the game reads back doesn't depend on the setting. Interpreter only - the JITs are unchanged, and none of this is reachable under them. Co-Authored-By: Claude Opus 5 <[email protected]> Claude-Session: https://claude.ai/code/session_01R9fKXvYBrnqtp1QQGaGWVv