mirror of
https://github.com/hrydgard/ppsspp.git
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478 lines
12 KiB
C++
478 lines
12 KiB
C++
// Copyright (c) 2012- PPSSPP Project.
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// This program is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation, version 2.0 or later versions.
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License 2.0 for more details.
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// A copy of the GPL 2.0 should have been included with the program.
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// If not, see http://www.gnu.org/licenses/
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// Official git repository and contact information can be found at
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// https://github.com/hrydgard/ppsspp and http://www.ppsspp.org/.
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#include <algorithm>
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#include "Core/MIPS/MIPS.h"
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#include "Core/MIPS/MIPSCodeUtils.h"
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#include "Core/MIPS/IR/IRJit.h"
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#include "Core/MIPS/IR/IRRegCache.h"
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#include "Common/CPUDetect.h"
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using namespace MIPSAnalyst;
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#define _RS MIPS_GET_RS(op)
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#define _RT MIPS_GET_RT(op)
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#define _RD MIPS_GET_RD(op)
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#define _FS MIPS_GET_FS(op)
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#define _FT MIPS_GET_FT(op)
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#define _FD MIPS_GET_FD(op)
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#define _SA MIPS_GET_SA(op)
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#define _POS ((op>> 6) & 0x1F)
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#define _SIZE ((op>>11) & 0x1F)
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#define _IMM16 (signed short)(op & 0xFFFF)
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#define _IMM26 (op & 0x03FFFFFF)
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// All functions should have CONDITIONAL_DISABLE, so we can narrow things down to a file quickly.
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// Currently known non working ones should have DISABLE.
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// #define CONDITIONAL_DISABLE { Comp_Generic(op); return; }
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#define CONDITIONAL_DISABLE ;
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#define DISABLE { Comp_Generic(op); return; }
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namespace MIPSComp {
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void IRJit::CompImmLogic(MIPSGPReg rs, MIPSGPReg rt, u32 uimm, IROp OP) {
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if (gpr.IsImm(rs)) {
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switch (OP) {
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case IROp::AddConst: gpr.SetImm(rt, gpr.GetImm(rs) + uimm); break;
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case IROp::SubConst: gpr.SetImm(rt, gpr.GetImm(rs) - uimm); break;
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case IROp::AndConst: gpr.SetImm(rt, gpr.GetImm(rs) & uimm); break;
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case IROp::OrConst: gpr.SetImm(rt, gpr.GetImm(rs) | uimm); break;
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case IROp::XorConst: gpr.SetImm(rt, gpr.GetImm(rs) ^ uimm); break;
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}
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} else {
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gpr.MapDirtyIn(rt, rs);
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ir.Write(OP, rt, rs, ir.AddConstant(uimm));
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}
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}
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void IRJit::Comp_IType(MIPSOpcode op) {
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CONDITIONAL_DISABLE;
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s32 simm = (s32)(s16)(op & 0xFFFF); // sign extension
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u32 uimm = op & 0xFFFF;
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u32 suimm = (u32)(s32)simm;
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MIPSGPReg rt = _RT;
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MIPSGPReg rs = _RS;
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// noop, won't write to ZERO.
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if (rt == 0)
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return;
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switch (op >> 26) {
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case 8: // same as addiu?
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case 9: // R(rt) = R(rs) + simm; break; //addiu
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// Special-case for small adjustments of pointerified registers. Commonly for SP but happens for others.
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if (simm >= 0) {
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CompImmLogic(rs, rt, simm, IROp::AddConst);
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} else if (simm < 0) {
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CompImmLogic(rs, rt, -simm, IROp::SubConst);
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}
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break;
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case 12: CompImmLogic(rs, rt, uimm, IROp::AndConst); break;
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case 13: CompImmLogic(rs, rt, uimm, IROp::OrConst); break;
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case 14: CompImmLogic(rs, rt, uimm, IROp::XorConst); break;
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case 10: // R(rt) = (s32)R(rs) < simm; break; //slti
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if (gpr.IsImm(rs)) {
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gpr.SetImm(rt, (s32)gpr.GetImm(rs) < simm ? 1 : 0);
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break;
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}
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gpr.MapDirtyIn(rt, rs);
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ir.Write(IROp::SltConst, rt, rs, ir.AddConstant(simm));
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break;
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case 11: // R(rt) = R(rs) < suimm; break; //sltiu
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if (gpr.IsImm(rs)) {
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gpr.SetImm(rt, gpr.GetImm(rs) < suimm ? 1 : 0);
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break;
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}
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gpr.MapDirtyIn(rt, rs);
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ir.Write(IROp::SltUConst, rt, rs, ir.AddConstant(suimm));
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break;
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case 15: // R(rt) = uimm << 16; //lui
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gpr.SetImm(rt, uimm << 16);
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break;
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default:
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Comp_Generic(op);
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break;
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}
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}
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void IRJit::Comp_RType2(MIPSOpcode op) {
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CONDITIONAL_DISABLE;
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MIPSGPReg rs = _RS;
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MIPSGPReg rd = _RD;
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// Don't change $zr.
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if (rd == 0)
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return;
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switch (op & 63) {
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case 22: //clz
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gpr.MapDirtyIn(rd, rs);
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ir.Write(IROp::Clz, rd, rs);
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break;
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case 23: //clo
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gpr.MapDirtyIn(rd, rs);
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ir.Write(IROp::Not, IRTEMP_0, rs);
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ir.Write(IROp::Clz, rd, IRTEMP_0);
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break;
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default:
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DISABLE;
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}
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}
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void IRJit::CompType3(MIPSGPReg rd, MIPSGPReg rs, MIPSGPReg rt, IROp op, IROp constOp, bool symmetric) {
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if (gpr.IsImm(rs) && gpr.IsImm(rt)) {
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switch (op) {
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case IROp::Add: gpr.SetImm(rd, gpr.GetImm(rs) + gpr.GetImm(rt)); break;
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case IROp::Sub: gpr.SetImm(rd, gpr.GetImm(rs) - gpr.GetImm(rt)); break;
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case IROp::And: gpr.SetImm(rd, gpr.GetImm(rs) & gpr.GetImm(rt)); break;
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case IROp::Or: gpr.SetImm(rd, gpr.GetImm(rs) | gpr.GetImm(rt)); break;
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case IROp::Xor: gpr.SetImm(rd, gpr.GetImm(rs) ^ gpr.GetImm(rt)); break;
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}
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return;
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}
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/*
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if (gpr.IsImm(rt) || (gpr.IsImm(rs) && symmetric)) {
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MIPSGPReg lhs = gpr.IsImm(rs) ? rt : rs;
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MIPSGPReg rhs = gpr.IsImm(rs) ? rs : rt;
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u32 rhsImm = gpr.GetImm(rhs);
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gpr.MapDirtyIn(rd, lhs);
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ir.Write(constOp, rd, lhs, ir.AddConstant(rhsImm));
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// If rd is rhs, we may have lost it in the MapDirtyIn(). lhs was kept.
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// This means the rhsImm value was never flushed to rhs, and would be garbage.
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if (rd == rhs) {
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// Luckily, it was just an imm.
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gpr.SetImm(rhs, rhsImm);
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}
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return;
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}*/
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// Can't do the RSB optimization on ARM64 - no RSB!
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// Generic solution. If it's an imm, better to flush at this point.
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gpr.MapDirtyInIn(rd, rs, rt);
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ir.Write(op, rd, rs, rt);
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}
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void IRJit::Comp_RType3(MIPSOpcode op) {
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CONDITIONAL_DISABLE;
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MIPSGPReg rt = _RT;
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MIPSGPReg rs = _RS;
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MIPSGPReg rd = _RD;
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// noop, won't write to ZERO.
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if (rd == 0)
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return;
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switch (op & 63) {
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case 10: //if (!R(rt)) R(rd) = R(rs); break; //movz
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gpr.MapDirtyInIn(rd, rt, rs);
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ir.Write(IROp::MovZ, rd, rt, rs);
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break;
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case 11:// if (R(rt)) R(rd) = R(rs); break; //movn
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gpr.MapDirtyInIn(rd, rt, rs);
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ir.Write(IROp::MovNZ, rd, rt, rs);
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break;
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case 32: //R(rd) = R(rs) + R(rt); break; //add
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case 33: //R(rd) = R(rs) + R(rt); break; //addu
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CompType3(rd, rs, rt, IROp::Add, IROp::AddConst, true);
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break;
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case 34: //R(rd) = R(rs) - R(rt); break; //sub
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case 35: //R(rd) = R(rs) - R(rt); break; //subu
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CompType3(rd, rs, rt, IROp::Sub, IROp::SubConst, false);
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break;
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case 36: //R(rd) = R(rs) & R(rt); break; //and
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CompType3(rd, rs, rt, IROp::And, IROp::AndConst, true);
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break;
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case 37: //R(rd) = R(rs) | R(rt); break; //or
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CompType3(rd, rs, rt, IROp::Or, IROp::OrConst, true);
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break;
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case 38: //R(rd) = R(rs) ^ R(rt); break; //xor/eor
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CompType3(rd, rs, rt, IROp::Xor, IROp::XorConst, true);
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break;
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case 39: // R(rd) = ~(R(rs) | R(rt)); break; //nor
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if (gpr.IsImm(rs) && gpr.IsImm(rt)) {
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gpr.SetImm(rd, ~(gpr.GetImm(rs) | gpr.GetImm(rt)));
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} else {
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gpr.MapDirtyInIn(rd, rs, rt);
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if (rs == 0) {
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ir.Write(IROp::Not, rd, rt);
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} else if (rt == 0) {
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ir.Write(IROp::Not, rd, rs);
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} else {
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ir.Write(IROp::Or, IRTEMP_0, rs, rt);
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ir.Write(IROp::Not, rd, IRTEMP_0);
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}
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}
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break;
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case 42: //R(rd) = (int)R(rs) < (int)R(rt); break; //slt
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if (gpr.IsImm(rs) && gpr.IsImm(rt)) {
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gpr.SetImm(rd, (s32)gpr.GetImm(rs) < (s32)gpr.GetImm(rt));
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} else {
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gpr.MapDirtyInIn(rd, rt, rs);
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ir.Write(IROp::Slt, rd, rs, rt);
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}
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break;
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case 43: //R(rd) = R(rs) < R(rt); break; //sltu
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if (gpr.IsImm(rs) && gpr.IsImm(rt)) {
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gpr.SetImm(rd, gpr.GetImm(rs) < gpr.GetImm(rt));
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} else {
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gpr.MapDirtyInIn(rd, rt, rs);
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ir.Write(IROp::SltU, rd, rs, rt);
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}
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break;
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case 44: //R(rd) = max(R(rs), R(rt); break; //max
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if (gpr.IsImm(rs) && gpr.IsImm(rt)) {
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gpr.SetImm(rd, std::max(gpr.GetImm(rs), gpr.GetImm(rt)));
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break;
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}
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gpr.MapDirtyInIn(rd, rs, rt);
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ir.Write(IROp::Max, rd, rs, rt);
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break;
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case 45: //R(rd) = min(R(rs), R(rt)); break; //min
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if (gpr.IsImm(rs) && gpr.IsImm(rt)) {
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gpr.SetImm(rd, std::min(gpr.GetImm(rs), gpr.GetImm(rt)));
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break;
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}
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gpr.MapDirtyInIn(rd, rs, rt);
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ir.Write(IROp::Min, rd, rs, rt);
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break;
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default:
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Comp_Generic(op);
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break;
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}
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}
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void IRJit::CompShiftImm(MIPSOpcode op, IROp shiftOpConst, int sa) {
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MIPSGPReg rd = _RD;
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MIPSGPReg rt = _RT;
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if (gpr.IsImm(rt)) {
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switch (shiftOpConst) {
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case IROp::ShlImm:
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gpr.SetImm(rd, gpr.GetImm(rt) << sa);
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break;
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case IROp::ShrImm:
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gpr.SetImm(rd, gpr.GetImm(rt) >> sa);
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break;
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case IROp::SarImm:
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gpr.SetImm(rd, (int)gpr.GetImm(rt) >> sa);
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break;
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case IROp::RorImm:
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gpr.SetImm(rd, (gpr.GetImm(rt) >> sa) | (gpr.GetImm(rt) << (32 - sa)));
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break;
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default:
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DISABLE;
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}
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} else {
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gpr.MapDirtyIn(rd, rt);
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ir.Write(shiftOpConst, rd, rt, sa);
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}
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}
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void IRJit::CompShiftVar(MIPSOpcode op, IROp shiftOp, IROp shiftOpConst) {
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MIPSGPReg rd = _RD;
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MIPSGPReg rt = _RT;
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MIPSGPReg rs = _RS;
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if (gpr.IsImm(rs)) {
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int sa = gpr.GetImm(rs) & 0x1F;
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CompShiftImm(op, shiftOpConst, sa);
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return;
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}
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gpr.MapDirtyInIn(rd, rs, rt);
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// Not sure if ARM64 wraps like this so let's do it for it. (TODO: According to the ARM ARM, it will indeed mask for us so this is not necessary)
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// ANDI2R(SCRATCH1, gpr.R(rs), 0x1F, INVALID_REG);
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ir.Write(IROp::AndConst, IRTEMP_0, rs, ir.AddConstant(31));
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ir.Write(shiftOp, rd, rt, IRTEMP_0);
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}
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void IRJit::Comp_ShiftType(MIPSOpcode op) {
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CONDITIONAL_DISABLE;
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MIPSGPReg rs = _RS;
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MIPSGPReg rd = _RD;
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int fd = _FD;
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int sa = _SA;
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// noop, won't write to ZERO.
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if (rd == 0)
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return;
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// WARNING : ROTR
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switch (op & 0x3f) {
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case 0: CompShiftImm(op, IROp::ShlImm, sa); break; //sll
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case 2: CompShiftImm(op, (rs == 1 ? IROp::RorImm : IROp::ShrImm), sa); break; //srl
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case 3: CompShiftImm(op, IROp::SarImm, sa); break; //sra
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case 4: CompShiftVar(op, IROp::Shl, IROp::ShlImm); break; //sllv
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case 6: CompShiftVar(op, (fd == 1 ? IROp::Ror : IROp::Shr), (fd == 1 ? IROp::RorImm : IROp::ShrImm)); break; //srlv
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case 7: CompShiftVar(op, IROp::Sar, IROp::SarImm); break; //srav
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default:
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DISABLE;
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break;
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}
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}
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void IRJit::Comp_Special3(MIPSOpcode op) {
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CONDITIONAL_DISABLE;
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MIPSGPReg rs = _RS;
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MIPSGPReg rt = _RT;
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int pos = _POS;
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int size = _SIZE + 1;
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u32 mask = 0xFFFFFFFFUL >> (32 - size);
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// Don't change $zr.
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if (rt == 0)
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return;
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switch (op & 0x3f) {
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case 0x0: //ext
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if (gpr.IsImm(rs)) {
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gpr.SetImm(rt, (gpr.GetImm(rs) >> pos) & mask);
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return;
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}
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gpr.MapDirtyIn(rt, rs);
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ir.Write(IROp::Shl, rt, rs);
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ir.Write(IROp::AndConst, rt, rt, ir.AddConstant(mask));
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break;
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case 0x4: //ins
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{
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u32 sourcemask = mask >> pos;
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u32 destmask = ~(sourcemask << pos);
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if (gpr.IsImm(rs)) {
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u32 inserted = (gpr.GetImm(rs) & sourcemask) << pos;
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if (gpr.IsImm(rt)) {
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gpr.SetImm(rt, (gpr.GetImm(rt) & destmask) | inserted);
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return;
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}
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gpr.MapDirty(rt);
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ir.Write(IROp::AndConst, rt, rt, ir.AddConstant(destmask));
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if (inserted != 0) {
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ir.Write(IROp::OrConst, rt, rt, inserted);
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}
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} else {
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gpr.MapDirtyIn(rt, rs);
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ir.Write(IROp::AndConst, IRTEMP_0, rs, ir.AddConstant(sourcemask));
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ir.Write(IROp::AndConst, rt, rt, ir.AddConstant(destmask));
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ir.Write(IROp::ShlImm, IRTEMP_0, IRTEMP_0, pos);
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ir.Write(IROp::Or, rt, rt, IRTEMP_0);
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}
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}
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break;
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}
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}
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void IRJit::Comp_Allegrex(MIPSOpcode op) {
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CONDITIONAL_DISABLE;
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MIPSGPReg rt = _RT;
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MIPSGPReg rd = _RD;
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// Don't change $zr.
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if (rd == 0)
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return;
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switch ((op >> 6) & 31) {
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case 16: // seb // R(rd) = (u32)(s32)(s8)(u8)R(rt);
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if (gpr.IsImm(rt)) {
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gpr.SetImm(rd, (s32)(s8)(u8)gpr.GetImm(rt));
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return;
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}
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gpr.MapDirtyIn(rd, rt);
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ir.Write(IROp::Ext8to32, rd, rt);
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break;
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case 24: // seh
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if (gpr.IsImm(rt)) {
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gpr.SetImm(rd, (s32)(s16)(u16)gpr.GetImm(rt));
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return;
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}
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gpr.MapDirtyIn(rd, rt);
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ir.Write(IROp::Ext16to32, rd, rt);
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break;
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case 20: //bitrev
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default:
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Comp_Generic(op);
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return;
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}
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}
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void IRJit::Comp_Allegrex2(MIPSOpcode op) {
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CONDITIONAL_DISABLE;
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MIPSGPReg rt = _RT;
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MIPSGPReg rd = _RD;
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// Don't change $zr.
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if (rd == 0)
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return;
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switch (op & 0x3ff) {
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case 0xA0: //wsbh
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if (gpr.IsImm(rt)) {
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gpr.SetImm(rd, ((gpr.GetImm(rt) & 0xFF00FF00) >> 8) | ((gpr.GetImm(rt) & 0x00FF00FF) << 8));
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} else {
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gpr.MapDirtyIn(rd, rt);
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ir.Write(IROp::BSwap16, rd, rt);
|
|
}
|
|
break;
|
|
case 0xE0: //wsbw
|
|
if (gpr.IsImm(rt)) {
|
|
gpr.SetImm(rd, swap32(gpr.GetImm(rt)));
|
|
} else {
|
|
gpr.MapDirtyIn(rd, rt);
|
|
ir.Write(IROp::BSwap16, rd, rt);
|
|
}
|
|
break;
|
|
default:
|
|
Comp_Generic(op);
|
|
break;
|
|
}
|
|
}
|
|
|
|
void IRJit::Comp_MulDivType(MIPSOpcode op) {
|
|
CONDITIONAL_DISABLE;
|
|
MIPSGPReg rt = _RT;
|
|
MIPSGPReg rs = _RS;
|
|
MIPSGPReg rd = _RD;
|
|
|
|
// Note that in all cases below, LO is actually mapped to HI:LO.
|
|
// That is, the host reg is 64 bits and has HI at the top.
|
|
// HI is not mappable.
|
|
|
|
DISABLE;
|
|
}
|
|
|
|
}
|