Henrik Rydgård d3e9398cb3 Split Core_EnableStepping into Core_Break and Core_Resume

2024-11-03 17:53:42 +01:00

..

RiscVAsm.cpp

Logging API change (refactor) (#19324)

2024-07-14 14:42:59 +02:00

RiscVCompALU.cpp

riscv: Use a single reg for LO/HI.

2023-08-20 14:49:09 -07:00

RiscVCompBranch.cpp

x86jit: Stub out op categories to files.

2023-08-20 22:28:54 -07:00

RiscVCompFPU.cpp

riscv: Implement Zfa encoding.

2023-12-29 09:42:23 -08:00

RiscVCompLoadStore.cpp

irjit: Fix safety of kernel bit memory addresses.

2023-09-24 10:18:55 -07:00

RiscVCompSystem.cpp

Split Core_EnableStepping into Core_Break and Core_Resume

2024-11-03 17:53:42 +01:00

RiscVCompVec.cpp

riscv: Implement Zfa encoding.

2023-12-29 09:42:23 -08:00

RiscVJit.cpp

Target->Native renaming. More intuitive (at least to me)

2024-07-22 01:24:34 +02:00

RiscVJit.h

Store IR instructions in a large arena vector instead of loosely in each block.

2024-06-07 09:28:27 +02:00

RiscVRegCache.cpp

Logging API change (refactor) (#19324)

2024-07-14 14:42:59 +02:00

RiscVRegCache.h

irjit: Add facility for native reg transfer.

2023-09-24 16:28:29 -07:00