mirror of
https://github.com/hrydgard/ppsspp.git
synced 2026-10-01 14:58:14 +00:00
Henrik RydgårdandClaude Opus 5.5
7eb371b231
Blocks ending in a branch dispatch a conditional exit and then the fallthrough ExitToConst. One op now returns either target, reading the second from the ExitToConst, which stays behind unexecuted. Co-Authored-By: Claude Opus 5.5 (1M context) <[email protected]>
539 lines
17 KiB
C++
539 lines
17 KiB
C++
// Copyright (c) 2022- PPSSPP Project.
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// This program is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation, version 2.0 or later versions.
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License 2.0 for more details.
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// A copy of the GPL 2.0 should have been included with the program.
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// If not, see http://www.gnu.org/licenses/
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// Official git repository and contact information can be found at
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// https://github.com/hrydgard/ppsspp and http://www.ppsspp.org/.
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#include <cstdio>
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#include <cstring>
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#include "Core/MIPS/IR/IRInst.h"
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#include "Core/Config.h"
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#include "Core/MIPS/IR/IRPassSimplify.h"
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struct IRVerification {
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const char *name;
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const std::vector<IRInst> input;
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const std::vector<IRInst> expected;
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const std::vector<IRPassFunc> passes;
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// Leaves lwl/lwr halves alone, among other things.
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bool optimizeForInterpreter = false;
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// ApplyMemoryValidation only runs without fast memory.
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bool slowMemory = false;
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};
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static void LogInstructions(const std::vector<IRInst> &insts) {
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for (size_t i = 0; i < insts.size(); ++i) {
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char buf[256];
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DisassembleIR(buf, sizeof(buf), insts[i]);
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printf(" %s\n", buf);
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}
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}
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static bool VerifyPass(const IRVerification &v) {
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IRWriter in, out;
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IROptions opts{};
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opts.unalignedLoadStore = true;
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opts.optimizeForInterpreter = v.optimizeForInterpreter;
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for (const auto &inst : v.input)
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in.Write(inst);
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const bool fastMemory = g_Config.bFastMemory;
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g_Config.bFastMemory = !v.slowMemory;
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bool logged = IRApplyPasses(v.passes.data(), v.passes.size(), in, out, opts);
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g_Config.bFastMemory = fastMemory;
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if (logged) {
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printf("%s FAILED: Unable to apply passes (or wanted to log)\n", v.name);
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return false;
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}
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const std::vector<IRInst> actual = out.GetInstructions();
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if (actual.size() != v.expected.size()) {
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printf("%s FAILED: produced %d instructions, expected %d\n", v.name, (int)actual.size(), (int)v.expected.size());
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printf("Actual:\n");
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LogInstructions(actual);
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printf("Expected:\n");
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LogInstructions(v.expected);
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return false;
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}
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for (size_t i = 0; i < actual.size(); ++i) {
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if (memcmp(&v.expected[i], &actual[i], sizeof(IRInst)) != 0) {
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char actualBuf[256];
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DisassembleIR(actualBuf, sizeof(actualBuf), actual[i]);
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char expectedBuf[256];
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DisassembleIR(expectedBuf, sizeof(expectedBuf), v.expected[i]);
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if (strcmp(expectedBuf, actualBuf) == 0) {
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// This means a field (like src2) was left set but isn't relevant. Ignore.
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continue;
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}
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printf("%s FAILED: #%d expected '%s' but was '%s'\n", v.name, (int)i, expectedBuf, actualBuf);
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printf("Actual:\n");
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LogInstructions(actual);
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return false;
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}
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}
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return true;
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}
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static const IRVerification tests[] = {
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{
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"SimplePurgeTemps",
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{
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{ IROp::Add, { IRTEMP_0 }, MIPS_REG_A0, MIPS_REG_A1 },
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{ IROp::Mov, { MIPS_REG_V0 }, IRTEMP_0 },
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{ IROp::Add, { IRTEMP_0 }, MIPS_REG_A2, MIPS_REG_A3 },
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{ IROp::Mov, { MIPS_REG_V1 }, IRTEMP_0 },
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},
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{
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{ IROp::Add, { MIPS_REG_V0 }, MIPS_REG_A0, MIPS_REG_A1 },
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{ IROp::Add, { MIPS_REG_V1 }, MIPS_REG_A2, MIPS_REG_A3 },
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},
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{ &PurgeTemps },
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},
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{
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"Load32LeftPurgeTemps",
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{
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{ IROp::Mov, { IRTEMP_LR_ADDR }, MIPS_REG_A0 },
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{ IROp::AndConst, { IRTEMP_LR_ADDR }, IRTEMP_LR_ADDR, 0, 0xFFFFFFFC },
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{ IROp::Load32, { MIPS_REG_V0 }, IRTEMP_LR_ADDR, 0, 0 },
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},
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{
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{ IROp::AndConst, { IRTEMP_LR_ADDR }, MIPS_REG_A0, 0, 0xFFFFFFFC },
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{ IROp::Load32, { MIPS_REG_V0 }, IRTEMP_LR_ADDR, 0, 0 },
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},
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{ &PurgeTemps },
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},
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{
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"SwapClobberTemp",
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{
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{ IROp::Sub, { MIPS_REG_A0 }, MIPS_REG_A1, MIPS_REG_A2 },
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{ IROp::Mov, { MIPS_REG_S0 }, MIPS_REG_A0 },
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{ IROp::Slt, { MIPS_REG_A0 }, MIPS_REG_V0, MIPS_REG_V1 },
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},
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{
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{ IROp::Sub, { MIPS_REG_S0 }, MIPS_REG_A1, MIPS_REG_A2 },
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{ IROp::Slt, { MIPS_REG_A0 }, MIPS_REG_V0, MIPS_REG_V1 },
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},
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{ &PurgeTemps },
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},
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{
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"DoubleClobberTemp",
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{
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{ IROp::Add, { MIPS_REG_A0 }, MIPS_REG_A1, MIPS_REG_A2 },
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{ IROp::Mov, { MIPS_REG_S0 }, MIPS_REG_A0 },
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{ IROp::Mov, { MIPS_REG_S0 }, MIPS_REG_A1 },
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},
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{
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{ IROp::Add, { MIPS_REG_S0 }, MIPS_REG_A1, MIPS_REG_A2 },
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{ IROp::Mov, { MIPS_REG_A0 }, MIPS_REG_S0 },
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{ IROp::Mov, { MIPS_REG_S0 }, MIPS_REG_A1 },
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},
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{ &PurgeTemps },
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},
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{
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"SimplePropagateConstants",
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{
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{ IROp::SetConst, { MIPS_REG_A0 }, 0, 0, 0x12340000 },
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{ IROp::OrConst, { MIPS_REG_A0 }, MIPS_REG_A0, 0, 0x00005678 },
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{ IROp::AddConst, { MIPS_REG_A1 }, MIPS_REG_A0, 0, 0 },
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{ IROp::AddConst, { MIPS_REG_A2 }, MIPS_REG_A0, 0, 0x00001111 },
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},
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{
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{ IROp::SetConst, { MIPS_REG_A0 }, 0, 0, 0x12345678 },
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{ IROp::SetConst, { MIPS_REG_A1 }, 0, 0, 0x12345678 },
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{ IROp::SetConst, { MIPS_REG_A2 }, 0, 0, 0x12346789 },
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},
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{ &PropagateConstants },
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},
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{
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// Needed for PurgeTemps optimizations to work.
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"OrToMov",
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{
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{ IROp::Sub, { MIPS_REG_A0 }, MIPS_REG_A1, MIPS_REG_A2 },
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{ IROp::Or, { MIPS_REG_S0 }, MIPS_REG_A0, MIPS_REG_ZERO },
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{ IROp::Add, { MIPS_REG_S1 }, MIPS_REG_A0, MIPS_REG_ZERO },
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{ IROp::OrConst, { MIPS_REG_S2 }, MIPS_REG_A0, 0, 0 },
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{ IROp::AddConst, { MIPS_REG_S3 }, MIPS_REG_A0, 0, 0 },
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},
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{
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{ IROp::Sub, { MIPS_REG_A0 }, MIPS_REG_A1, MIPS_REG_A2 },
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{ IROp::Mov, { MIPS_REG_S0 }, MIPS_REG_A0 },
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{ IROp::Mov, { MIPS_REG_S1 }, MIPS_REG_A0 },
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{ IROp::Mov, { MIPS_REG_S2 }, MIPS_REG_A0 },
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{ IROp::Mov, { MIPS_REG_S3 }, MIPS_REG_A0 },
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},
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{ &PropagateConstants },
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},
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{
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// The FNeg reads the temp and overwrites it, so the FAdd must see the negation.
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"PurgeTempsFPRRewrittenInPlace",
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{
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{ IROp::FMov, { IRVTEMP_PFX_S }, 5 },
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{ IROp::FNeg, { IRVTEMP_PFX_S }, IRVTEMP_PFX_S },
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{ IROp::FAdd, { 0 }, IRVTEMP_PFX_S, 1 },
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},
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{
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{ IROp::FNeg, { IRVTEMP_PFX_S }, 5 },
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{ IROp::FAdd, { 0 }, IRVTEMP_PFX_S, 1 },
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},
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{ &PurgeTemps },
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},
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{
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"PurgeTempsFPRReadTwice",
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{
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{ IROp::FMov, { IRVTEMP_PFX_S }, 5 },
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{ IROp::FMul, { 0 }, IRVTEMP_PFX_S, IRVTEMP_PFX_S },
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},
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{
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{ IROp::FMul, { 0 }, 5, 5 },
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},
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{ &PurgeTemps },
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},
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{
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// The FPR temp has the same number as IRTEMP_0, which is the address here.
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"PurgeTempsFPRStoreSrc3",
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{
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{ IROp::FMov, { IRVTEMP_PFX_S }, 5 },
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{ IROp::StoreFloat, { IRVTEMP_PFX_S }, IRTEMP_0, 0, 0x10 },
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},
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{
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{ IROp::StoreFloat, { 5 }, IRTEMP_0, 0, 0x10 },
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},
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{ &PurgeTemps },
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},
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{
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// The FMov writes lane 1 of the temp between its write and the Vec4Mov.
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"PurgeTempsVec4LaneWrite",
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{
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{ IROp::Vec4Add, { IRVTEMP_0 }, 32, 36 },
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{ IROp::FMov, { IRVTEMP_0 + 1 }, 20 },
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{ IROp::Vec4Mov, { 48 }, IRVTEMP_0 },
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},
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{
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{ IROp::Vec4Add, { IRVTEMP_0 }, 32, 36 },
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{ IROp::FMov, { IRVTEMP_0 + 1 }, 20 },
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{ IROp::Vec4Mov, { 48 }, IRVTEMP_0 },
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},
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{ &PurgeTemps },
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},
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{
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// The Vec4Scale reads 48 before the Vec4Mov writes it.
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"PurgeTempsVec4ScaleRead",
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{
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{ IROp::Vec4Add, { IRVTEMP_0 }, 32, 36 },
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{ IROp::Vec4Scale, { 40 }, 48, 1 },
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{ IROp::Vec4Mov, { 48 }, IRVTEMP_0 },
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},
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{
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{ IROp::Vec4Add, { IRVTEMP_0 }, 32, 36 },
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{ IROp::Vec4Scale, { 40 }, 48, 1 },
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{ IROp::Vec4Mov, { 48 }, IRVTEMP_0 },
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},
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{ &PurgeTemps },
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},
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{
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// Writing 48 before the exit would change it on the path that exits.
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"PurgeTempsSwapAcrossExit",
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{
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{ IROp::Vec4Add, { IRVTEMP_0 }, 32, 36 },
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{ IROp::ExitToConstIfEq, { 0 }, MIPS_REG_A0, MIPS_REG_A1, 0x08804000 },
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{ IROp::Vec4Mov, { 48 }, IRVTEMP_0 },
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},
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{
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{ IROp::Vec4Add, { IRVTEMP_0 }, 32, 36 },
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{ IROp::ExitToConstIfEq, { 0 }, MIPS_REG_A0, MIPS_REG_A1, 0x08804000 },
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{ IROp::Vec4Mov, { 48 }, IRVTEMP_0 },
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},
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{ &PurgeTemps },
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},
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{
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// sc stores and ll sets LLBIT, so neither goes away when the reg is overwritten.
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"PurgeTempsKeepsLLSC",
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{
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{ IROp::Load32Linked, { MIPS_REG_V1 }, MIPS_REG_A0, 0, 0 },
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{ IROp::SetConst, { MIPS_REG_V1 }, 0, 0, 1 },
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{ IROp::Store32Conditional, { MIPS_REG_V0 }, MIPS_REG_A0, 0, 0 },
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{ IROp::SetConst, { MIPS_REG_V0 }, 0, 0, 1 },
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},
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{
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{ IROp::Load32Linked, { MIPS_REG_V1 }, MIPS_REG_A0, 0, 0 },
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{ IROp::SetConst, { MIPS_REG_V1 }, 0, 0, 1 },
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{ IROp::Store32Conditional, { MIPS_REG_V0 }, MIPS_REG_A0, 0, 0 },
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{ IROp::SetConst, { MIPS_REG_V0 }, 0, 0, 1 },
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},
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{ &PurgeTemps },
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},
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{
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"CombineLoadLeftRight",
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{
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{ IROp::Load32Left, { MIPS_REG_A0 }, MIPS_REG_A1, 0, 3 },
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{ IROp::Load32Right, { MIPS_REG_A0 }, MIPS_REG_A1, 0, 0 },
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},
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{
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{ IROp::Load32, { MIPS_REG_A0 }, MIPS_REG_A1, 0, 0 },
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},
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{ &RemoveLoadStoreLeftRight },
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true,
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},
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{
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// The lwl changes a0, so the lwr reads from a different address.
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"NoCombineLoadLeftRightIntoBase",
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{
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{ IROp::Load32Left, { MIPS_REG_A0 }, MIPS_REG_A0, 0, 3 },
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{ IROp::Load32Right, { MIPS_REG_A0 }, MIPS_REG_A0, 0, 0 },
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},
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{
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{ IROp::Load32Left, { MIPS_REG_A0 }, MIPS_REG_A0, 0, 3 },
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{ IROp::Load32Right, { MIPS_REG_A0 }, MIPS_REG_A0, 0, 0 },
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},
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{ &RemoveLoadStoreLeftRight },
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true,
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},
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{
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// The sp accesses share one validation, but not across something that may change sp.
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"ValidateSPAcrossInterpret",
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{
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{ IROp::Load32, { MIPS_REG_A0 }, MIPS_REG_SP, 0, 0 },
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{ IROp::Interpret, { 0 }, 0, 0, 0 },
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{ IROp::Load32, { MIPS_REG_A1 }, MIPS_REG_SP, 0, 8 },
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},
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{
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{ IROp::ValidateAddress32, { 0 }, MIPS_REG_SP, 0, 0 },
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{ IROp::Load32, { MIPS_REG_A0 }, MIPS_REG_SP, 0, 0 },
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{ IROp::Interpret, { 0 }, 0, 0, 0 },
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{ IROp::ValidateAddress32, { 0 }, MIPS_REG_SP, 0, 8 },
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{ IROp::Load32, { MIPS_REG_A1 }, MIPS_REG_SP, 0, 8 },
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},
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{ &ApplyMemoryValidation },
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false,
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true,
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},
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{
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"PropagateConstantsPastFSat",
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{
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{ IROp::SetConst, { MIPS_REG_A0 }, 0, 0, 0x100 },
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{ IROp::FSat0_1, { 1 }, 1 },
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{ IROp::Add, { MIPS_REG_A1 }, MIPS_REG_A0, MIPS_REG_A0 },
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},
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{
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{ IROp::FSat0_1, { 1 }, 1 },
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{ IROp::SetConst, { MIPS_REG_A0 }, 0, 0, 0x100 },
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{ IROp::SetConst, { MIPS_REG_A1 }, 0, 0, 0x200 },
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},
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{ &PropagateConstants },
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},
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{
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// lui v0, hi; lw v0, lo(v0)
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"PropagateConstantsLoadIntoBase",
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{
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{ IROp::SetConst, { MIPS_REG_V0 }, 0, 0, 0x08810000 },
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{ IROp::Load32, { MIPS_REG_V0 }, MIPS_REG_V0, 0, 0x20 },
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},
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{
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{ IROp::Load32, { MIPS_REG_V0 }, MIPS_REG_ZERO, 0, 0x08810020 },
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},
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{ &PropagateConstants },
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},
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{
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// The store writes a0 out, and it stays known.
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"PropagateConstantsPastStore",
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{
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{ IROp::SetConst, { MIPS_REG_A0 }, 0, 0, 5 },
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{ IROp::Store32, { MIPS_REG_A0 }, MIPS_REG_SP, 0, 0 },
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{ IROp::AddConst, { MIPS_REG_A1 }, MIPS_REG_A0, 0, 0x20 },
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},
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{
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{ IROp::SetConst, { MIPS_REG_A0 }, 0, 0, 5 },
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{ IROp::Store32, { MIPS_REG_A0 }, MIPS_REG_SP, 0, 0 },
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{ IROp::SetConst, { MIPS_REG_A1 }, 0, 0, 0x25 },
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},
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{ &PropagateConstants },
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},
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{
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"PropagateConstantsPastCondExit",
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{
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{ IROp::SetConst, { MIPS_REG_A0 }, 0, 0, 5 },
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{ IROp::ExitToConstIfEq, { 0 }, MIPS_REG_A1, MIPS_REG_A2, 0x08804000 },
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{ IROp::AddConst, { MIPS_REG_A3 }, MIPS_REG_A0, 0, 1 },
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},
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{
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{ IROp::SetConst, { MIPS_REG_A0 }, 0, 0, 5 },
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{ IROp::ExitToConstIfEq, { 0 }, MIPS_REG_A1, MIPS_REG_A2, 0x08804000 },
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{ IROp::SetConst, { MIPS_REG_A3 }, 0, 0, 6 },
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},
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{ &PropagateConstants },
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},
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{
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// Each of these may change a0 after reading it.
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"PropagateConstantsReadThenWritten",
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{
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{ IROp::SetConst, { MIPS_REG_A0 }, 0, 0, 5 },
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{ IROp::MovZ, { MIPS_REG_A0 }, MIPS_REG_A1, MIPS_REG_A2 },
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{ IROp::AddConst, { MIPS_REG_T0 }, MIPS_REG_A0, 0, 1 },
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{ IROp::SetConst, { MIPS_REG_A0 }, 0, 0, 5 },
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{ IROp::Store32Conditional, { MIPS_REG_A0 }, MIPS_REG_A1, 0, 0 },
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{ IROp::AddConst, { MIPS_REG_T1 }, MIPS_REG_A0, 0, 1 },
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{ IROp::SetConst, { MIPS_REG_A0 }, 0, 0, 5 },
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{ IROp::Load32Left, { MIPS_REG_A0 }, MIPS_REG_A1, 0, 3 },
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{ IROp::AddConst, { MIPS_REG_T2 }, MIPS_REG_A0, 0, 1 },
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},
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{
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{ IROp::SetConst, { MIPS_REG_A0 }, 0, 0, 5 },
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{ IROp::MovZ, { MIPS_REG_A0 }, MIPS_REG_A1, MIPS_REG_A2 },
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{ IROp::AddConst, { MIPS_REG_T0 }, MIPS_REG_A0, 0, 1 },
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{ IROp::SetConst, { MIPS_REG_A0 }, 0, 0, 5 },
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{ IROp::Store32Conditional, { MIPS_REG_A0 }, MIPS_REG_A1, 0, 0 },
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{ IROp::AddConst, { MIPS_REG_T1 }, MIPS_REG_A0, 0, 1 },
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{ IROp::SetConst, { MIPS_REG_A0 }, 0, 0, 5 },
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{ IROp::Load32Left, { MIPS_REG_A0 }, MIPS_REG_A1, 0, 3 },
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{ IROp::AddConst, { MIPS_REG_T2 }, MIPS_REG_A0, 0, 1 },
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},
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{ &PropagateConstants },
|
|
},
|
|
{
|
|
// The exit is always taken, so nothing after it runs.
|
|
"PropagateConstantsTakenExit",
|
|
{
|
|
{ IROp::SetConst, { MIPS_REG_A0 }, 0, 0, 0 },
|
|
{ IROp::ExitToConstIfEq, { 0 }, MIPS_REG_A0, MIPS_REG_ZERO, 0x08804000 },
|
|
{ IROp::Downcount, { 0 }, 0, 0, 4 },
|
|
{ IROp::ExitToConst, { 0 }, 0, 0, 0x08804100 },
|
|
},
|
|
{
|
|
{ IROp::SetConst, { MIPS_REG_A0 }, 0, 0, 0 },
|
|
{ IROp::ExitToConst, { 0 }, 0, 0, 0x08804000 },
|
|
},
|
|
{ &PropagateConstants },
|
|
},
|
|
{
|
|
"ForwardStoresToLoads",
|
|
{
|
|
{ IROp::Store32, { MIPS_REG_A0 }, MIPS_REG_SP, 0, 0x10 },
|
|
{ IROp::Add, { MIPS_REG_T0 }, MIPS_REG_T1, MIPS_REG_T2 },
|
|
{ IROp::Load32, { MIPS_REG_A1 }, MIPS_REG_SP, 0, 0x10 },
|
|
{ IROp::StoreFloat, { 1 }, MIPS_REG_SP, 0, 0x20 },
|
|
{ IROp::LoadFloat, { 2 }, MIPS_REG_SP, 0, 0x20 },
|
|
{ IROp::Store32, { MIPS_REG_A0 }, MIPS_REG_SP, 0, 0x30 },
|
|
{ IROp::LoadFloat, { 3 }, MIPS_REG_SP, 0, 0x30 },
|
|
{ IROp::Store8, { MIPS_REG_A2 }, MIPS_REG_SP, 0, 0x40 },
|
|
{ IROp::Load8Ext, { MIPS_REG_A3 }, MIPS_REG_SP, 0, 0x40 },
|
|
{ IROp::StoreVec4, { 32 }, MIPS_REG_SP, 0, 0x50 },
|
|
{ IROp::LoadVec4, { 36 }, MIPS_REG_SP, 0, 0x50 },
|
|
{ IROp::Load32, { MIPS_REG_T3 }, MIPS_REG_GP, 0, 0x100 },
|
|
{ IROp::Load32, { MIPS_REG_T4 }, MIPS_REG_GP, 0, 0x100 },
|
|
// Disjoint on the same base, so the first is still known.
|
|
{ IROp::Store32, { MIPS_REG_S0 }, MIPS_REG_S1, 0, 0x20 },
|
|
{ IROp::Store32, { MIPS_REG_S2 }, MIPS_REG_S1, 0, 0x24 },
|
|
{ IROp::Load32, { MIPS_REG_S3 }, MIPS_REG_S1, 0, 0x20 },
|
|
// Already in the reg.
|
|
{ IROp::Load32, { MIPS_REG_S2 }, MIPS_REG_S1, 0, 0x24 },
|
|
},
|
|
{
|
|
{ IROp::Store32, { MIPS_REG_A0 }, MIPS_REG_SP, 0, 0x10 },
|
|
{ IROp::Add, { MIPS_REG_T0 }, MIPS_REG_T1, MIPS_REG_T2 },
|
|
{ IROp::Mov, { MIPS_REG_A1 }, MIPS_REG_A0 },
|
|
{ IROp::StoreFloat, { 1 }, MIPS_REG_SP, 0, 0x20 },
|
|
{ IROp::FMov, { 2 }, 1 },
|
|
{ IROp::Store32, { MIPS_REG_A0 }, MIPS_REG_SP, 0, 0x30 },
|
|
{ IROp::FMovFromGPR, { 3 }, MIPS_REG_A0 },
|
|
{ IROp::Store8, { MIPS_REG_A2 }, MIPS_REG_SP, 0, 0x40 },
|
|
{ IROp::Ext8to32, { MIPS_REG_A3 }, MIPS_REG_A2 },
|
|
{ IROp::StoreVec4, { 32 }, MIPS_REG_SP, 0, 0x50 },
|
|
{ IROp::Vec4Mov, { 36 }, 32 },
|
|
{ IROp::Load32, { MIPS_REG_T3 }, MIPS_REG_GP, 0, 0x100 },
|
|
{ IROp::Mov, { MIPS_REG_T4 }, MIPS_REG_T3 },
|
|
{ IROp::Store32, { MIPS_REG_S0 }, MIPS_REG_S1, 0, 0x20 },
|
|
{ IROp::Store32, { MIPS_REG_S2 }, MIPS_REG_S1, 0, 0x24 },
|
|
{ IROp::Mov, { MIPS_REG_S3 }, MIPS_REG_S0 },
|
|
},
|
|
{ &OptimizeLoadsAfterStores },
|
|
},
|
|
{
|
|
"NoForwardStoresToLoads",
|
|
{
|
|
// A store through another base may alias.
|
|
{ IROp::Store32, { MIPS_REG_A0 }, MIPS_REG_SP, 0, 0 },
|
|
{ IROp::Store32, { MIPS_REG_A1 }, MIPS_REG_A2, 0, 0 },
|
|
{ IROp::Load32, { MIPS_REG_A3 }, MIPS_REG_SP, 0, 0 },
|
|
// The value reg changed.
|
|
{ IROp::Store32, { MIPS_REG_T0 }, MIPS_REG_SP, 0, 4 },
|
|
{ IROp::AddConst, { MIPS_REG_T0 }, MIPS_REG_T0, 0, 1 },
|
|
{ IROp::Load32, { MIPS_REG_T1 }, MIPS_REG_SP, 0, 4 },
|
|
// An overlapping narrow store.
|
|
{ IROp::Store32, { MIPS_REG_T2 }, MIPS_REG_SP, 0, 0x10 },
|
|
{ IROp::Store16, { MIPS_REG_T3 }, MIPS_REG_SP, 0, 0x12 },
|
|
{ IROp::Load32, { MIPS_REG_T4 }, MIPS_REG_SP, 0, 0x10 },
|
|
// The Interpret may do anything.
|
|
{ IROp::Store32, { MIPS_REG_S0 }, MIPS_REG_SP, 0, 0x20 },
|
|
{ IROp::Interpret, { 0 }, 0, 0, 0 },
|
|
{ IROp::Load32, { MIPS_REG_S1 }, MIPS_REG_SP, 0, 0x20 },
|
|
// Not RAM, so maybe a hardware register.
|
|
{ IROp::Store32, { MIPS_REG_S2 }, MIPS_REG_ZERO, 0, 0xBC100000 },
|
|
{ IROp::Load32, { MIPS_REG_S3 }, MIPS_REG_ZERO, 0, 0xBC100000 },
|
|
// The base reg changed.
|
|
{ IROp::Store32, { MIPS_REG_S4 }, MIPS_REG_SP, 0, 0x30 },
|
|
{ IROp::AddConst, { MIPS_REG_SP }, MIPS_REG_SP, 0, 0xFFFFFFF0 },
|
|
{ IROp::Load32, { MIPS_REG_S5 }, MIPS_REG_SP, 0, 0x30 },
|
|
},
|
|
{
|
|
{ IROp::Store32, { MIPS_REG_A0 }, MIPS_REG_SP, 0, 0 },
|
|
{ IROp::Store32, { MIPS_REG_A1 }, MIPS_REG_A2, 0, 0 },
|
|
{ IROp::Load32, { MIPS_REG_A3 }, MIPS_REG_SP, 0, 0 },
|
|
{ IROp::Store32, { MIPS_REG_T0 }, MIPS_REG_SP, 0, 4 },
|
|
{ IROp::AddConst, { MIPS_REG_T0 }, MIPS_REG_T0, 0, 1 },
|
|
{ IROp::Load32, { MIPS_REG_T1 }, MIPS_REG_SP, 0, 4 },
|
|
{ IROp::Store32, { MIPS_REG_T2 }, MIPS_REG_SP, 0, 0x10 },
|
|
{ IROp::Store16, { MIPS_REG_T3 }, MIPS_REG_SP, 0, 0x12 },
|
|
{ IROp::Load32, { MIPS_REG_T4 }, MIPS_REG_SP, 0, 0x10 },
|
|
{ IROp::Store32, { MIPS_REG_S0 }, MIPS_REG_SP, 0, 0x20 },
|
|
{ IROp::Interpret, { 0 }, 0, 0, 0 },
|
|
{ IROp::Load32, { MIPS_REG_S1 }, MIPS_REG_SP, 0, 0x20 },
|
|
{ IROp::Store32, { MIPS_REG_S2 }, MIPS_REG_ZERO, 0, 0xBC100000 },
|
|
{ IROp::Load32, { MIPS_REG_S3 }, MIPS_REG_ZERO, 0, 0xBC100000 },
|
|
{ IROp::Store32, { MIPS_REG_S4 }, MIPS_REG_SP, 0, 0x30 },
|
|
{ IROp::AddConst, { MIPS_REG_SP }, MIPS_REG_SP, 0, 0xFFFFFFF0 },
|
|
{ IROp::Load32, { MIPS_REG_S5 }, MIPS_REG_SP, 0, 0x30 },
|
|
},
|
|
{ &OptimizeLoadsAfterStores },
|
|
},
|
|
{
|
|
"InterpreterExitElse",
|
|
{
|
|
{ IROp::ExitToConstIfLtZ, { 0 }, MIPS_REG_A0, 0, 0x08804000 },
|
|
{ IROp::ExitToConst, { 0 }, 0, 0, 0x08804100 },
|
|
},
|
|
{
|
|
{ IROp::Downcount, { 0 }, 0, 0, 0 },
|
|
{ IROp::OptExitToConstIfLtZElse, { 0 }, MIPS_REG_A0, 0, 0x08804000 },
|
|
{ IROp::ExitToConst, { 0 }, 0, 0, 0x08804100 },
|
|
},
|
|
{ &OptimizeForInterpreter },
|
|
},
|
|
};
|
|
|
|
bool TestIRPassSimplify() {
|
|
InitIR();
|
|
|
|
bool success = true;
|
|
for (const auto &test : tests) {
|
|
if (!VerifyPass(test))
|
|
success = false;
|
|
}
|
|
|
|
return success;
|
|
}
|