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23 Commits
Author SHA1 Message Date
Henrik RydgårdandClaude Opus 5.5 eaf55c467b IR: Fold ClampToZero into the 31-bit packs 
Vec4ClampToZero and Vec2ClampToZero only ever fed Vec4Pack31To8 and
Vec2Pack31To16, for vi2uc and vi2us. The packs now clamp negative lanes
to zero themselves, which saves an op and a vector temp, and lets x64
clamp with PACKUSWB's saturation after an arithmetic shift.

While at it, RISC-V compiles Vec2Unpack16To31, Vec2Pack31To16 and
Vec4Pack32To8, and LoongArch Vec2Unpack16To31, Vec2Pack31To16 and the
non-LSX Vec4Pack32To8, all of which went to the IR interpreter.
LoongArch's Vec2Pack32To16 and Vec2Unpack16To32 now take their scalar
path with LSX too, instead of falling back.

Co-Authored-By: Claude Opus 5.5 (1M context) <[email protected]>
 2026-09-24 14:31:22 -06:00
Unknown W. Brackets 15cb782f85 riscv: Implement Zfa encoding. 
Not yet enabled/detected.
 2023-12-29 09:42:23 -08:00
Unknown W. Brackets 81aeb04788 arm64jit: Implement Vec4Blend. 2023-09-05 00:10:26 -07:00
Unknown W. Brackets 9439a43323 riscv: Correct an overlap case, fix assert. 2023-09-03 13:29:57 -07:00
Unknown W. Brackets 6a75e6712e riscv: Use automapping for special cases too. 2023-08-20 12:42:11 -07:00
Unknown W. Brackets a190793ad2 riscv: Simplify mapping for more instructions. 2023-08-20 12:42:11 -07:00
Unknown W. Brackets f9bf7de701 riscv: Use a single reg cache. 2023-08-20 12:42:11 -07:00
Unknown W. Brackets a23ade8f75 riscv: Map IR regs based on metadata. 
Only doing this in places without GPR/FPR mix or FPR/Vec overlap for now.
 2023-08-20 12:42:11 -07:00
Unknown W. Brackets 4e41f83ecc riscv: Centralize IR reg cache metadata checks. 
These are all largely the same between backends.
 2023-08-17 23:03:31 -07:00
Unknown W. Brackets b30daa5760 riscv: Centralize state of regcaches. 2023-08-15 21:51:38 -07:00
Unknown W. Brackets 52cc38bf2a riscv: Implement vs2i. 2023-08-13 18:27:19 -07:00
Henrik Rydgård 2342c4522c Merge pull request #17875 from unknownbrackets/riscv-jit 
RISC-V: Implement a few more ops
 2023-08-09 09:30:15 +02:00
Unknown W. Brackets 2c13b6d973 riscv: Implement vc2i. 2023-08-08 23:17:32 -07:00
Unknown W. Brackets ddf3d02a3c riscv: Implement vi2uc. 2023-08-08 23:17:32 -07:00
Unknown W. Brackets 1a92027810 riscv: Make Vec4Shuffle overlap safe. 2023-08-08 23:00:45 -07:00
Unknown W. Brackets 79ca880ac7 irjit: Implement vqmul, add Vec4Blend. 
Should be useful more places.
 2023-08-06 13:38:00 -07:00
Unknown W. Brackets 93e3d35f5d irjit: Move more to IRNativeBackend, split. 2023-08-06 00:16:43 -07:00
Unknown W. Brackets 921bd2391c riscv: Implement vi2s. 2023-07-29 19:02:15 -07:00
Unknown W. Brackets 0c9dce8ba8 riscv: Implement vec4 dot. 2023-07-25 20:33:56 -07:00
Unknown W. Brackets 23e9dffc68 riscv: Implement vec4 shuffle and init. 2023-07-25 20:33:56 -07:00
Unknown W. Brackets 4e17c59cc2 riscv: Implement simple vec4 ops via floats. 2023-07-25 20:33:56 -07:00
Unknown W. Brackets c2da7d18bb riscv: Stub out more IR compilation categories. 2023-07-23 18:01:00 -07:00
Unknown W. Brackets bf7a6eb2cd riscv: Add jit for some initial instructions. 2023-07-23 18:01:00 -07:00