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arm64 JIT: Compile vh2f, vt4444/5551/5650, vbfy, vmscl, vcrs and vdet
All went to the interpreter. vh2f works in integers to match vfpu_h2f, since FCVTL neither flushes subnormal halves nor keeps inf/NaN mantissa bits unshifted. The color conversions are bitfield extracts and inserts. vbfy, vcrs and vdet follow the IR frontend, and vmscl scales element by element. Results go through scratch registers, so a destination that overlaps a source is fine. Co-Authored-By: Claude Opus 5.5 (1M context) <[email protected]>
This commit is contained in:
Henrik RydgårdandClaude Opus 5.5 committed
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commit
ebd279fa70
1 file changed
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-40
@@ -1049,52 +1049,60 @@ namespace MIPSComp {
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}
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void Arm64Jit::Comp_Vh2f(MIPSOpcode op) {
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// TODO: Fix by porting the general SSE solution to NEON
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// FCVTL doesn't provide identical results to the PSP hardware, according to the unit test:
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// O vh2f: 00000000,400c0000,00000000,7ff00000
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// E vh2f: 00000000,400c0000,00000000,7f800380
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DISABLE;
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CONDITIONAL_DISABLE(VFPU_VEC);
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if (js.HasUnknownPrefix()) {
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if (js.HasUnknownPrefix() || !IsPrefixWithinSize(js.prefixS, op)) {
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DISABLE;
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}
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// Half to float, in integers to match vfpu_h2f: a zero exponent (subnormals included) gives a
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// signed zero, and inf/NaN keep their mantissa bits unshifted. FCVTL does neither.
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VectorSize sz = GetVecSize(op);
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if (sz != V_Single && sz != V_Pair) {
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DISABLE;
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}
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const int nIn = sz == V_Single ? 1 : 2;
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const VectorSize outSz = sz == V_Single ? V_Pair : V_Quad;
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u8 sregs[4], dregs[4];
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VectorSize sz = GetVecSize(op);
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VectorSize outSz;
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switch (sz) {
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case V_Single:
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outSz = V_Pair;
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break;
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case V_Pair:
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outSz = V_Quad;
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break;
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default:
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DISABLE;
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}
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int n = GetNumVectorElements(sz);
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int nOut = n * 2;
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GetVectorRegsPrefixS(sregs, sz, _VS);
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GetVectorRegsPrefixD(dregs, outSz, _VD);
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// Take the single registers and combine them to a D register.
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for (int i = 0; i < n; i++) {
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fpr.MapRegV(sregs[i], sz);
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fp.INS(32, Q0, i, fpr.V(sregs[i]), 0);
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}
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// Convert four 16-bit floats in D0 to four 32-bit floats in Q0 (even if we only have two...)
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fp.FCVTL(32, Q0, D0);
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// Split apart again.
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for (int i = 0; i < nOut; i++) {
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fpr.MapRegV(dregs[i], MAP_DIRTY | MAP_NOINIT);
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fp.INS(32, fpr.V(dregs[i]), 0, Q0, i);
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const ARM64Reg t = gpr.GetAndLockTempR();
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const ARM64Reg t2 = gpr.GetAndLockTempR();
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// Into S0-S3 first, since d may overlap s.
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for (int i = 0; i < nIn * 2; i++) {
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const ARM64Reg h = SCRATCH1, res = SCRATCH2;
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fpr.MapRegV(sregs[i / 2]);
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fp.FMOV(h, fpr.V(sregs[i / 2]));
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if (i & 1) {
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LSR(h, h, 16);
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} else {
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UBFX(h, h, 0, 16);
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}
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// Normal: ((h & 0x7FFF) << 13) + (112 << 23), then the sign.
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UBFIZ(res, h, 13, 15);
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MOVI2R(t, 0x38000000);
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ADD(res, res, t);
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UBFX(t, h, 10, 5);
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CMPI2R(t, 0);
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CSEL(res, WZR, res, CC_EQ);
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CMPI2R(t, 31);
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ANDI2R(t2, h, 0x3FF);
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ORRI2R(t2, t2, 0x7F800000);
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CSEL(res, t2, res, CC_EQ);
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UBFX(t, h, 15, 1);
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ORR(res, res, t, ArithOption(t, ST_LSL, 31));
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fp.FMOV((ARM64Reg)(S0 + i), res);
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}
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ApplyPrefixD(dregs, sz);
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for (int i = 0; i < nIn * 2; i++) {
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fpr.MapRegV(dregs[i], MAP_DIRTY | MAP_NOINIT);
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fp.FMOV(fpr.V(dregs[i]), (ARM64Reg)(S0 + i));
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}
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ApplyPrefixD(dregs, outSz);
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fpr.ReleaseSpillLocksAndDiscardTemps();
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gpr.ReleaseSpillLocksAndDiscardTemps();
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}
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void Arm64Jit::Comp_Vf2i(MIPSOpcode op) {
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@@ -1444,7 +1452,34 @@ namespace MIPSComp {
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}
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void Arm64Jit::Comp_Vmscl(MIPSOpcode op) {
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DISABLE;
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CONDITIONAL_DISABLE(VFPU_MTX_VMSCL);
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if (!js.HasNoPrefix()) {
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DISABLE;
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}
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// Matrix scale: d[N,M] = s[N,M] * t[0]. Element-wise, so transposition doesn't matter, but a
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// source that partly overlaps the destination would be read after it's written.
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MatrixSize sz = GetMtxSize(op);
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int n = GetMatrixSide(sz);
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if (_VS != _VD && GetMatrixOverlap(_VS, _VD, sz) != OVERLAP_NONE) {
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DISABLE;
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}
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u8 sregs[16], dregs[16], treg;
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GetMatrixRegs(sregs, sz, _VS);
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GetMatrixRegs(dregs, sz, _VD);
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GetVectorRegs(&treg, V_Single, _VT);
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// The scale can be part of the destination, so keep a copy.
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fpr.MapRegV(treg);
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fp.FMOV(S0, fpr.V(treg));
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for (int a = 0; a < n; a++) {
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for (int b = 0; b < n; b++) {
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fpr.MapDirtyInV(dregs[a * 4 + b], sregs[a * 4 + b]);
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fp.FMUL(fpr.V(dregs[a * 4 + b]), fpr.V(sregs[a * 4 + b]), S0);
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}
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}
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fpr.ReleaseSpillLocksAndDiscardTemps();
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}
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void Arm64Jit::Comp_Vtfm(MIPSOpcode op) {
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@@ -1513,11 +1548,66 @@ namespace MIPSComp {
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}
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void Arm64Jit::Comp_VCrs(MIPSOpcode op) {
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DISABLE;
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CONDITIONAL_DISABLE(VFPU_VEC);
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if (js.HasUnknownPrefix() || js.HasSPrefix() || js.HasTPrefix()) {
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DISABLE;
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}
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// Half a cross product: d[0] = s[y]*t[z], d[1] = s[z]*t[x], d[2] = s[x]*t[y].
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VectorSize sz = GetVecSize(op);
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if (sz != V_Triple) {
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DISABLE;
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}
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u8 sregs[4], tregs[4], dregs[4];
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GetVectorRegsPrefixS(sregs, sz, _VS);
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GetVectorRegsPrefixT(tregs, sz, _VT);
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GetVectorRegsPrefixD(dregs, sz, _VD);
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// Into S0-S2 first, since d may overlap s or t.
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fpr.MapRegsAndSpillLockV(sregs, sz, 0);
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fpr.MapRegsAndSpillLockV(tregs, sz, 0);
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fp.FMUL(S0, fpr.V(sregs[1]), fpr.V(tregs[2]));
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fp.FMUL(S1, fpr.V(sregs[2]), fpr.V(tregs[0]));
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fp.FMUL(S2, fpr.V(sregs[0]), fpr.V(tregs[1]));
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fpr.MapRegsAndSpillLockV(dregs, sz, MAP_NOINIT);
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for (int i = 0; i < 3; i++) {
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fp.FMOV(fpr.V(dregs[i]), (ARM64Reg)(S0 + i));
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}
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ApplyPrefixD(dregs, sz);
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fpr.ReleaseSpillLocksAndDiscardTemps();
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}
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void Arm64Jit::Comp_VDet(MIPSOpcode op) {
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DISABLE;
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CONDITIONAL_DISABLE(VFPU_VEC);
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if (js.HasUnknownPrefix() || !IsPrefixWithinSize(js.prefixS, op) || js.HasTPrefix()) {
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DISABLE;
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}
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// 2D determinant of two vectors: d[0] = s[0]*t[1] - s[1]*t[0].
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VectorSize sz = GetVecSize(op);
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if (sz != V_Pair) {
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DISABLE;
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}
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u8 sregs[4], tregs[4], dregs[4];
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GetVectorRegsPrefixS(sregs, sz, _VS);
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GetVectorRegsPrefixT(tregs, sz, _VT);
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GetVectorRegsPrefixD(dregs, V_Single, _VD);
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fpr.MapRegsAndSpillLockV(sregs, sz, 0);
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fpr.MapRegsAndSpillLockV(tregs, sz, 0);
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fp.FMUL(S1, fpr.V(sregs[1]), fpr.V(tregs[0]));
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fp.FMUL(S0, fpr.V(sregs[0]), fpr.V(tregs[1]));
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fp.FSUB(S0, S0, S1);
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fpr.MapRegV(dregs[0], MAP_DIRTY | MAP_NOINIT);
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fp.FMOV(fpr.V(dregs[0]), S0);
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ApplyPrefixD(dregs, V_Single);
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fpr.ReleaseSpillLocksAndDiscardTemps();
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}
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void Arm64Jit::Comp_Vi2x(MIPSOpcode op) {
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@@ -2267,11 +2357,119 @@ namespace MIPSComp {
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}
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void Arm64Jit::Comp_ColorConv(MIPSOpcode op) {
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DISABLE;
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CONDITIONAL_DISABLE(VFPU_VEC);
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if (js.HasUnknownPrefix() || !IsPrefixWithinSize(js.prefixS, op) || js.HasTPrefix()) {
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DISABLE;
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}
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// vt4444, vt5551, vt5650: four 8888 colors from a quad, whatever the size, into 16 bits each,
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// two to a word.
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const int type = (op >> 16) & 3;
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if (type == 0) {
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DISABLE;
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}
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VectorSize isz = GetVecSize(op);
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VectorSize outSz = isz == V_Single ? V_Single : V_Pair;
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u8 sregs[4], dregs[4];
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GetVectorRegsPrefixS(sregs, V_Quad, _VS);
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GetVectorRegsPrefixD(dregs, outSz, _VD);
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const ARM64Reg t = gpr.GetAndLockTempR();
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const ARM64Reg word = gpr.GetAndLockTempR();
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const ARM64Reg in = SCRATCH1, col = SCRATCH2;
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// Into S0-S1 first, since d may overlap s.
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for (int i = 0; i < 4; i++) {
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fpr.MapRegV(sregs[i]);
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fp.FMOV(in, fpr.V(sregs[i]));
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switch (type) {
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case 1: // 4444: the top four bits of each channel.
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UBFX(col, in, 4, 4);
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UBFX(t, in, 12, 4);
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BFI(col, t, 4, 4);
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UBFX(t, in, 20, 4);
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BFI(col, t, 8, 4);
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UBFX(t, in, 28, 4);
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BFI(col, t, 12, 4);
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break;
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case 2: // 5551
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UBFX(col, in, 3, 5);
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UBFX(t, in, 11, 5);
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BFI(col, t, 5, 5);
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UBFX(t, in, 19, 5);
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BFI(col, t, 10, 5);
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UBFX(t, in, 31, 1);
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BFI(col, t, 15, 1);
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break;
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case 3: // 565, no alpha.
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UBFX(col, in, 3, 5);
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UBFX(t, in, 10, 6);
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BFI(col, t, 5, 6);
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UBFX(t, in, 19, 5);
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BFI(col, t, 11, 5);
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break;
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}
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if ((i & 1) == 0) {
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MOV(word, col);
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} else {
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BFI(word, col, 16, 16);
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fp.FMOV((ARM64Reg)(S0 + i / 2), word);
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}
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}
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const int nOut = outSz == V_Single ? 1 : 2;
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for (int i = 0; i < nOut; i++) {
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fpr.MapRegV(dregs[i], MAP_DIRTY | MAP_NOINIT);
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fp.FMOV(fpr.V(dregs[i]), (ARM64Reg)(S0 + i));
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}
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ApplyPrefixD(dregs, outSz);
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fpr.ReleaseSpillLocksAndDiscardTemps();
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gpr.ReleaseSpillLocksAndDiscardTemps();
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}
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void Arm64Jit::Comp_Vbfy(MIPSOpcode op) {
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DISABLE;
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CONDITIONAL_DISABLE(VFPU_VEC);
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if (js.HasUnknownPrefix() || !IsPrefixWithinSize(js.prefixS, op) || js.HasTPrefix() || (js.prefixS & VFPU_NEGATE(1, 1, 1, 1)) != 0) {
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DISABLE;
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}
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// Butterfly. vbfy1: d[2N] = s[2N] + s[2N+1], d[2N+1] = s[2N] - s[2N+1].
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// vbfy2: d[0] = s[0] + s[2], d[1] = s[1] + s[3], d[2] = s[0] - s[2], d[3] = s[1] - s[3].
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VectorSize sz = GetVecSize(op);
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int n = GetNumVectorElements(sz);
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const int subop = (op >> 16) & 0x1F;
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if (!(subop == 3 && n == 4) && !(subop == 2 && (n == 2 || n == 4))) {
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DISABLE;
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}
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u8 sregs[4], dregs[4];
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GetVectorRegsPrefixS(sregs, sz, _VS);
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GetVectorRegsPrefixD(dregs, sz, _VD);
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// Into S0-S3 first, since d may overlap s.
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fpr.MapRegsAndSpillLockV(sregs, sz, 0);
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if (subop == 3) {
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fp.FADD(S0, fpr.V(sregs[0]), fpr.V(sregs[2]));
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fp.FADD(S1, fpr.V(sregs[1]), fpr.V(sregs[3]));
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fp.FSUB(S2, fpr.V(sregs[0]), fpr.V(sregs[2]));
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fp.FSUB(S3, fpr.V(sregs[1]), fpr.V(sregs[3]));
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} else {
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fp.FADD(S0, fpr.V(sregs[0]), fpr.V(sregs[1]));
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fp.FSUB(S1, fpr.V(sregs[0]), fpr.V(sregs[1]));
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if (n == 4) {
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fp.FADD(S2, fpr.V(sregs[2]), fpr.V(sregs[3]));
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fp.FSUB(S3, fpr.V(sregs[2]), fpr.V(sregs[3]));
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}
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}
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fpr.MapRegsAndSpillLockV(dregs, sz, MAP_NOINIT);
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for (int i = 0; i < n; i++) {
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fp.FMOV(fpr.V(dregs[i]), (ARM64Reg)(S0 + i));
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}
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ApplyPrefixD(dregs, sz);
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fpr.ReleaseSpillLocksAndDiscardTemps();
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}
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}
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