From a34e32abe10573ca81a06b77159dcfd64f0a44e0 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Henrik=20Rydg=C3=A5rd?= Date: Tue, 11 Oct 2022 15:42:59 +0200 Subject: [PATCH] Revert "Disables "ForceCheck" on jit invalidation on ARM32, introduced in #16194" This reverts commit bc28f546126e8d275e8c891dc6d7f4faefc7668e. --- Core/CoreTiming.cpp | 2 -- Core/MIPS/JitCommon/JitState.cpp | 2 +- Core/MIPS/MIPS.cpp | 4 ---- 3 files changed, 1 insertion(+), 7 deletions(-) diff --git a/Core/CoreTiming.cpp b/Core/CoreTiming.cpp index c75db0a08f..da24649553 100644 --- a/Core/CoreTiming.cpp +++ b/Core/CoreTiming.cpp @@ -585,8 +585,6 @@ void ForceCheck() int cyclesExecuted = slicelength - currentMIPS->downcount; globalTimer += cyclesExecuted; // This will cause us to check for new events immediately. - // NOTE: This causes problems on ARM32 in certain contexts due to jo.downcountInRegister. - // Not 100% sure what's going on there yet. currentMIPS->downcount = -1; // But let's not eat a bunch more time in Advance() because of this. slicelength = -1; diff --git a/Core/MIPS/JitCommon/JitState.cpp b/Core/MIPS/JitCommon/JitState.cpp index 6da26656c2..0326519245 100644 --- a/Core/MIPS/JitCommon/JitState.cpp +++ b/Core/MIPS/JitCommon/JitState.cpp @@ -37,7 +37,7 @@ namespace MIPSComp { // ARM only downcountInRegister = true; - useNEONVFPU = false; + useNEONVFPU = false; // true if (Disabled(JitDisable::SIMD)) useNEONVFPU = false; diff --git a/Core/MIPS/MIPS.cpp b/Core/MIPS/MIPS.cpp index b31dfe63e2..5aeeacbbf8 100644 --- a/Core/MIPS/MIPS.cpp +++ b/Core/MIPS/MIPS.cpp @@ -370,9 +370,7 @@ void MIPSState::InvalidateICache(u32 address, int length) { if (coreState == CORE_RUNNING || insideJit) { pendingClears.emplace_back(address, length); hasPendingClears = true; -#if !PPSSPP_ARCH(ARM) // See comment in ForceCheck CoreTiming::ForceCheck(); -#endif } else { MIPSComp::jit->InvalidateCacheAt(address, length); } @@ -385,9 +383,7 @@ void MIPSState::ClearJitCache() { if (coreState == CORE_RUNNING || insideJit) { pendingClears.emplace_back(0, 0); hasPendingClears = true; -#if !PPSSPP_ARCH(ARM) // See comment in ForceCheck CoreTiming::ForceCheck(); -#endif } else { MIPSComp::jit->ClearCache(); }