VFPU: Fix vrot with the angle in a destination lane

The cosine is then taken of what vrot wrote to that lane: the sine, or zero.
The IR looked at the sine lane instead of the lane holding the angle, and the
legacy JITs ignored the overlap. The assembler refuses such a vrot, so those
now leave it to the interpreter, and don't pair one with the vrot before it.

Covered by the new cpu/vfpu/vrot test.

Co-Authored-By: Claude Opus 5.5 (1M context) <[email protected]>

test.py

@@ -102,6 +102,7 @@ tests_good = [
   "cpu/vfpu/matrix",
   "cpu/vfpu/vavg",
   "cpu/vfpu/exact",
+  "cpu/vfpu/vrot",
   "cpu/icache/icache",
   "cpu/lsu/lsu",
   "cpu/lsu/llsc",