Mirror/ppsspp
1
0 Fork 0
mirror of https://github.com/hrydgard/ppsspp.git synced 2026-10-01 14:58:14 +00:00
Code Issues Packages Projects Releases Wiki Activity

ARM JITs: Mask what ctc1 writes to fcr31

Browse Source 
Only the rounding mode, flags, enables, cause, FCC and FS bits can be
written (0x0181FFFF, pspautotests cpu/fpu/fcr), as the interpreter, IR
and x86 already have it. Both ARM JITs stored the whole value.

Co-Authored-By: Claude Opus 5.5 (1M context) <[email protected]>
This commit is contained in:
Henrik RydgårdandClaude Opus 5.5 committed 2026-09-29 11:09:47 -06:00
1 parent 178186ef4e
commit 5865a560eb
2 files changed
+6 -6
Download Patch File Download Diff File Expand all files Collapse all files

No files matched your search

Core/MIPS/ARM/ArmCompFPU.cpp
+3 -3
View File
@@ -431,9 +431,9 @@ void ArmJit::Comp_mxc1(MIPSOpcode op)
gpr.MapDirtyIn(MIPS_REG_FPCOND, rt);
}
// Update MIPS state
// TODO: Technically, should mask by 0x0181FFFF. Maybe just put all of FCR31 in the reg?
STR(gpr.R(rt), CTXREG, offsetof(MIPSState, fcr31));
// Update MIPS state. Only these bits can be written (pspautotests cpu/fpu/fcr).
ANDI2R(SCRATCHREG1, gpr.R(rt), 0x0181FFFF, SCRATCHREG2);
STR(SCRATCHREG1, CTXREG, offsetof(MIPSState, fcr31));
if (!wasImm) {
#if PPSSPP_ARCH(ARMV7)
UBFX(gpr.R(MIPS_REG_FPCOND), gpr.R(rt), 23, 1);
Core/MIPS/ARM64/Arm64CompFPU.cpp
+3 -3
View File
@@ -396,9 +396,9 @@ void Arm64Jit::Comp_mxc1(MIPSOpcode op)
gpr.MapDirtyIn(MIPS_REG_FPCOND, rt);
}
// Update MIPS state
// TODO: Technically, should mask by 0x0181FFFF. Maybe just put all of FCR31 in the reg?
STR(INDEX_UNSIGNED, gpr.R(rt), CTXREG, offsetof(MIPSState, fcr31));
// Update MIPS state. Only these bits can be written (pspautotests cpu/fpu/fcr).
ANDI2R(SCRATCH1, gpr.R(rt), 0x0181FFFF, SCRATCH2);
STR(INDEX_UNSIGNED, SCRATCH1, CTXREG, offsetof(MIPSState, fcr31));
if (!wasImm) {
UBFX(gpr.R(MIPS_REG_FPCOND), gpr.R(rt), 23, 1);
// TODO: We do have the fcr31 value in a register here, could use that in UpdateRoundingMode to avoid reloading it.